ixgbe: Refactor MSI-X allocation mechanism
Our current MSI-X allocation mechanism does not support new hardware at all. It also isn't getting the actual number of supported MSI-X vectors from the device. This patch allows the number of MSI-X vectors to be specific to a device, plus it gets the number of MSI-X vectors available from PCIe configuration space. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2f21bdd354
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4 changed files with 42 additions and 3 deletions
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@ -204,9 +204,13 @@ struct ixgbe_q_vector {
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#define OTHER_VECTOR 1
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#define OTHER_VECTOR 1
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#define NON_Q_VECTORS (OTHER_VECTOR)
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#define NON_Q_VECTORS (OTHER_VECTOR)
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#define MAX_MSIX_Q_VECTORS 16
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#define MAX_MSIX_VECTORS_82598 18
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#define MAX_MSIX_Q_VECTORS_82598 16
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#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82598
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#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82598
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#define MIN_MSIX_Q_VECTORS 2
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#define MIN_MSIX_Q_VECTORS 2
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#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
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#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
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#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
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/* board specific private data structure */
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/* board specific private data structure */
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@ -244,6 +248,7 @@ struct ixgbe_adapter {
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u64 hw_csum_rx_good;
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u64 hw_csum_rx_good;
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u64 non_eop_descs;
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u64 non_eop_descs;
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int num_msix_vectors;
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int num_msix_vectors;
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int max_msix_q_vectors; /* true count of q_vectors for device */
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struct ixgbe_ring_feature ring_feature[3];
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struct ixgbe_ring_feature ring_feature[3];
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struct msix_entry *msix_entries;
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struct msix_entry *msix_entries;
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@ -49,6 +49,27 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
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static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data);
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u8 *eeprom_data);
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/**
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* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
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* @hw: pointer to hardware structure
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*
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* Read PCIe configuration space, and get the MSI-X vector count from
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* the capabilities table.
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**/
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u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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u16 msix_count;
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pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
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&msix_count);
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msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
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/* MSI-X count is zero-based in HW, so increment to give proper value */
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msix_count++;
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return msix_count;
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}
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/**
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/**
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*/
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*/
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static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
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static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
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@ -106,6 +127,7 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
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mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
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mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
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mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
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mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
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mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
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mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
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mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
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out:
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out:
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return ret_val;
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return ret_val;
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@ -2421,7 +2421,13 @@ static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
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ixgbe_set_num_queues(adapter);
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ixgbe_set_num_queues(adapter);
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} else {
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} else {
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adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
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adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
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adapter->num_msix_vectors = vectors;
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/*
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* Adjust for only the vectors we'll use, which is minimum
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* of max_msix_q_vectors + NON_Q_VECTORS, or the number of
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* vectors we were allocated.
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*/
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adapter->num_msix_vectors = min(vectors,
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adapter->max_msix_q_vectors + NON_Q_VECTORS);
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}
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}
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}
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}
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@ -2746,6 +2752,7 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
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adapter->ring_feature[RING_F_RSS].indices = rss;
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adapter->ring_feature[RING_F_RSS].indices = rss;
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adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
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adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
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adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
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adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
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adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
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#ifdef CONFIG_IXGBE_DCB
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#ifdef CONFIG_IXGBE_DCB
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/* Configure DCB traffic classes */
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/* Configure DCB traffic classes */
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@ -821,6 +821,10 @@
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#define IXGBE_FW_PTR 0x0F
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#define IXGBE_FW_PTR 0x0F
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#define IXGBE_PBANUM0_PTR 0x15
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#define IXGBE_PBANUM0_PTR 0x15
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#define IXGBE_PBANUM1_PTR 0x16
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#define IXGBE_PBANUM1_PTR 0x16
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#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
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/* MSI-X capability fields masks */
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#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
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/* Legacy EEPROM word offsets */
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/* Legacy EEPROM word offsets */
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#define IXGBE_ISCSI_BOOT_CAPS 0x0033
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#define IXGBE_ISCSI_BOOT_CAPS 0x0033
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@ -1451,6 +1455,7 @@ struct ixgbe_mac_info {
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u32 num_rar_entries;
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u32 num_rar_entries;
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u32 max_tx_queues;
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u32 max_tx_queues;
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u32 max_rx_queues;
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u32 max_rx_queues;
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u32 max_msix_vectors;
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u32 link_attach_type;
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u32 link_attach_type;
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u32 link_mode_select;
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u32 link_mode_select;
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bool link_settings_loaded;
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bool link_settings_loaded;
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