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Merge 3.4-rc5 into driver-core-next 

This was done to resolve a merge issue with the init/main.c file.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2012-05-02 14:33:37 -07:00
parent aac10aaa8c 69964ea4c7
commit eb1574270a
811 changed files with 7637 additions and 5445 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Documentation/ABI/stable/sysfs-driver-usb-usbtmc
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@ -1,5 +1,5 @@
What: /sys/bus/usb/drivers/usbtmc/devices/*/interface_capabilities
What: /sys/bus/usb/drivers/usbtmc/devices/*/device_capabilities
What: /sys/bus/usb/drivers/usbtmc/*/interface_capabilities
What: /sys/bus/usb/drivers/usbtmc/*/device_capabilities
Date: August 2008
Contact: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Description:
@ -12,8 +12,8 @@ Description:
The files are read only.
What: /sys/bus/usb/drivers/usbtmc/devices/*/usb488_interface_capabilities
What: /sys/bus/usb/drivers/usbtmc/devices/*/usb488_device_capabilities
What: /sys/bus/usb/drivers/usbtmc/*/usb488_interface_capabilities
What: /sys/bus/usb/drivers/usbtmc/*/usb488_device_capabilities
Date: August 2008
Contact: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Description:
@ -27,7 +27,7 @@ Description:
The files are read only.
What: /sys/bus/usb/drivers/usbtmc/devices/*/TermChar
What: /sys/bus/usb/drivers/usbtmc/*/TermChar
Date: August 2008
Contact: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Description:
@ -40,7 +40,7 @@ Description:
sent to the device or not.
What: /sys/bus/usb/drivers/usbtmc/devices/*/TermCharEnabled
What: /sys/bus/usb/drivers/usbtmc/*/TermCharEnabled
Date: August 2008
Contact: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Description:
@ -51,7 +51,7 @@ Description:
published by the USB-IF.
What: /sys/bus/usb/drivers/usbtmc/devices/*/auto_abort
What: /sys/bus/usb/drivers/usbtmc/*/auto_abort
Date: August 2008
Contact: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Description:

18
Documentation/ABI/testing/sysfs-block-rssd Normal file
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@ -0,0 +1,18 @@
What: /sys/block/rssd*/registers
Date: March 2012
KernelVersion: 3.3
Contact: Asai Thambi S P <asamymuthupa@micron.com>
Description: This is a read-only file. Dumps below driver information and
hardware registers.
- S ACTive
- Command Issue
- Allocated
- Completed
- PORT IRQ STAT
- HOST IRQ STAT
What: /sys/block/rssd*/status
Date: April 2012
KernelVersion: 3.4
Contact: Asai Thambi S P <asamymuthupa@micron.com>
Description: This is a read-only file. Indicates the status of the device.

19
Documentation/ABI/testing/sysfs-bus-hsi Normal file
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@ -0,0 +1,19 @@
What: /sys/bus/hsi
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description:
High Speed Synchronous Serial Interface (HSI) is a
serial interface mainly used for connecting application
engines (APE) with cellular modem engines (CMT) in cellular
handsets.
The bus will be populated with devices (hsi_clients) representing
the protocols available in the system. Bus drivers implement
those protocols.
What: /sys/bus/hsi/devices/.../modalias
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description: Stores the same MODALIAS value emitted by uevent
Format: hsi:<hsi_client device name>

8
Documentation/ABI/testing/sysfs-cfq-target-latency Normal file
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@ -0,0 +1,8 @@
What: /sys/block/<device>/iosched/target_latency
Date: March 2012
contact: Tao Ma <boyu.mt@taobao.com>
Description:
The /sys/block/<device>/iosched/target_latency only exists
when the user sets cfq to /sys/block/<device>/scheduler.
It contains an estimated latency time for the cfq. cfq will
use it to calculate the time slice used for every task.

2
Documentation/DocBook/media/v4l/pixfmt-nv12m.xml
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@ -1,6 +1,6 @@
<refentry id="V4L2-PIX-FMT-NV12M">
<refmeta>
<refentrytitle>V4L2_PIX_FMT_NV12M ('NV12M')</refentrytitle>
<refentrytitle>V4L2_PIX_FMT_NV12M ('NM12')</refentrytitle>
&manvol;
</refmeta>
<refnamediv>

2
Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml
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@ -1,6 +1,6 @@
<refentry id="V4L2-PIX-FMT-YUV420M">
<refmeta>
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YU12M')</refentrytitle>
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YM12')</refentrytitle>
&manvol;
</refmeta>
<refnamediv>

5
Documentation/cgroups/memory.txt
View File

@ -34,8 +34,7 @@ Current Status: linux-2.6.34-mmotm(development version of 2010/April)
Features:
- accounting anonymous pages, file caches, swap caches usage and limiting them.
- private LRU and reclaim routine. (system's global LRU and private LRU
work independently from each other)
- pages are linked to per-memcg LRU exclusively, and there is no global LRU.
- optionally, memory+swap usage can be accounted and limited.
- hierarchical accounting
- soft limit
@ -154,7 +153,7 @@ updated. page_cgroup has its own LRU on cgroup.
2.2.1 Accounting details
All mapped anon pages (RSS) and cache pages (Page Cache) are accounted.
Some pages which are never reclaimable and will not be on the global LRU
Some pages which are never reclaimable and will not be on the LRU
are not accounted. We just account pages under usual VM management.
RSS pages are accounted at page_fault unless they've already been accounted

8
Documentation/feature-removal-schedule.txt
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@ -538,3 +538,11 @@ Why: There appear to be no production users of the get_robust_list syscall,
of ASLR. It was only ever intended for debugging, so it should be
removed.
Who: Kees Cook <keescook@chromium.org>
----------------------------
What: setitimer accepts user NULL pointer (value)
When: 3.6
Why: setitimer is not returning -EFAULT if user pointer is NULL. This
violates the spec.
Who: Sasikantha Babu <sasikanth.v19@gmail.com>

2
Documentation/filesystems/vfs.txt
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@ -114,7 +114,7 @@ members are defined:
struct file_system_type {
const char *name;
int fs_flags;
struct dentry (*mount) (struct file_system_type *, int,
struct dentry *(*mount) (struct file_system_type *, int,
const char *, void *);
void (*kill_sb) (struct super_block *);
struct module *owner;

37
Documentation/power/freezing-of-tasks.txt
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@ -9,7 +9,7 @@ architectures).
II. How does it work?
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
PF_NOFREEZE unset (all user space processes and some kernel threads) are
regarded as 'freezable' and treated in a special way before the system enters a
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
we only consider hibernation, but the description also applies to suspend).
Namely, as the first step of the hibernation procedure the function
freeze_processes() (defined in kernel/power/process.c) is called. It executes
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
either wakes them up, if they are kernel threads, or sends fake signals to them,
if they are user space processes. A task that has TIF_FREEZE set, should react
to it by calling the function called __refrigerator() (defined in
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
Then, we say that the task is 'frozen' and therefore the set of functions
handling this mechanism is referred to as 'the freezer' (these functions are
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
User space processes are generally frozen before kernel threads.
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
whether the system is to undergo a freezing operation. And freeze_processes()
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
fake signal to all user space processes, and wakes up all the kernel threads.
All freezable tasks must react to that by calling try_to_freeze(), which
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
'frozen' and therefore the set of functions handling this mechanism is referred
to as 'the freezer' (these functions are defined in kernel/power/process.c,
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
frozen before kernel threads.
__refrigerator() must not be called directly. Instead, use the
try_to_freeze() function (defined in include/linux/freezer.h), that checks
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
flag is set.
if the task is to be frozen and makes the task enter __refrigerator().
For user space processes try_to_freeze() is called automatically from the
signal-handling code, but the freezable kernel threads need to call it
explicitly in suitable places or use the wait_event_freezable() or
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
try_to_freeze(). The main loop of a freezable kernel thread may look like the
following one:
that combine interruptible sleep with checking if the task is to be frozen and
calling try_to_freeze(). The main loop of a freezable kernel thread may look
like the following one:
set_freezable();
do {
@ -53,7 +54,7 @@ following one:
(from drivers/usb/core/hub.c::hub_thread()).
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
initiated a freezing operation, the freezing of tasks will fail and the entire
hibernation operation will be cancelled. For this reason, freezable kernel
threads must call try_to_freeze() somewhere or use one of the
wait_event_freezable() and wait_event_freezable_timeout() macros.

14
Documentation/security/keys.txt
View File

@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
The key service provides a number of features besides keys:
(*) The key service defines two special key types:
(*) The key service defines three special key types:
(+) "keyring"
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
blobs of data. These can be created, updated and read by userspace,
and aren't intended for use by kernel services.
(+) "logon"
Like a "user" key, a "logon" key has a payload that is an arbitrary
blob of data. It is intended as a place to store secrets which are
accessible to the kernel but not to userspace programs.
The description can be arbitrary, but must be prefixed with a non-zero
length string that describes the key "subclass". The subclass is
separated from the rest of the description by a ':'. "logon" keys can
be created and updated from userspace, but the payload is only
readable from kernel space.
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
process-specific keyring, and a session-specific keyring.

4
Documentation/sound/alsa/HD-Audio-Models.txt
View File

@ -43,7 +43,9 @@ ALC680
ALC882/883/885/888/889
======================
N/A
acer-aspire-4930g Acer Aspire 4930G/5930G/6530G/6930G/7730G
acer-aspire-8930g Acer Aspire 8330G/6935G
acer-aspire Acer Aspire others
ALC861/660
==========

22
Documentation/usb/URB.txt
View File

@ -168,6 +168,28 @@ that if the completion handler or anyone else tries to resubmit it
they will get a -EPERM error. Thus you can be sure that when
usb_kill_urb() returns, the URB is totally idle.
There is a lifetime issue to consider. An URB may complete at any
time, and the completion handler may free the URB. If this happens
while usb_unlink_urb or usb_kill_urb is running, it will cause a
memory-access violation. The driver is responsible for avoiding this,
which often means some sort of lock will be needed to prevent the URB
from being deallocated while it is still in use.
On the other hand, since usb_unlink_urb may end up calling the
completion handler, the handler must not take any lock that is held
when usb_unlink_urb is invoked. The general solution to this problem
is to increment the URB's reference count while holding the lock, then
drop the lock and call usb_unlink_urb or usb_kill_urb, and then
decrement the URB's reference count. You increment the reference
count by calling
struct urb *usb_get_urb(struct urb *urb)
(ignore the return value; it is the same as the argument) and
decrement the reference count by calling usb_free_urb. Of course,
none of this is necessary if there's no danger of the URB being freed
by the completion handler.
1.7. What about the completion handler?

6
Documentation/usb/usbmon.txt
View File

@ -183,10 +183,10 @@ An input control transfer to get a port status.
d5ea89a0 3575914555 S Ci:1:001:0 s a3 00 0000 0003 0004 4 <
d5ea89a0 3575914560 C Ci:1:001:0 0 4 = 01050000
An output bulk transfer to send a SCSI command 0x5E in a 31-byte Bulk wrapper
to a storage device at address 5:
An output bulk transfer to send a SCSI command 0x28 (READ_10) in a 31-byte
Bulk wrapper to a storage device at address 5:
dd65f0e8 4128379752 S Bo:1:005:2 -115 31 = 55534243 5e000000 00000000 00000600 00000000 00000000 00000000 000000
dd65f0e8 4128379752 S Bo:1:005:2 -115 31 = 55534243 ad000000 00800000 80010a28 20000000 20000040 00000000 000000
dd65f0e8 4128379808 C Bo:1:005:2 0 31 >
* Raw binary format and API

30
MAINTAINERS
View File

@ -1521,8 +1521,8 @@ M: Gustavo Padovan <gustavo@padovan.org>
M: Johan Hedberg <johan.hedberg@gmail.com>
L: linux-bluetooth@vger.kernel.org
W: http://www.bluez.org/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/padovan/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jh/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git
S: Maintained
F: drivers/bluetooth/
@ -1532,8 +1532,8 @@ M: Gustavo Padovan <gustavo@padovan.org>
M: Johan Hedberg <johan.hedberg@gmail.com>
L: linux-bluetooth@vger.kernel.org
W: http://www.bluez.org/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/padovan/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jh/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git
S: Maintained
F: net/bluetooth/
F: include/net/bluetooth/
@ -2321,9 +2321,9 @@ S: Supported
F: drivers/acpi/dock.c
DOCUMENTATION
M: Randy Dunlap <rdunlap@xenotime.net>
M: Rob Landley <rob@landley.net>
L: linux-doc@vger.kernel.org
T: quilt http://xenotime.net/kernel-doc-patches/current/
T: TBD
S: Maintained
F: Documentation/
@ -3592,6 +3592,7 @@ S: Supported
F: drivers/net/wireless/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Johannes Berg <johannes.berg@intel.com>
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
@ -4533,8 +4534,7 @@ S: Supported
F: drivers/net/ethernet/myricom/myri10ge/
NATSEMI ETHERNET DRIVER (DP8381x)
M: Tim Hockin <thockin@hockin.org>
S: Maintained
S: Orphan
F: drivers/net/ethernet/natsemi/natsemi.c
NATIVE INSTRUMENTS USB SOUND INTERFACE DRIVER
@ -4803,6 +4803,7 @@ F: arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
F: arch/arm/mach-omap2/clockdomain44xx.c
OMAP AUDIO SUPPORT
M: Peter Ujfalusi <peter.ujfalusi@ti.com>
M: Jarkko Nikula <jarkko.nikula@bitmer.com>
L: alsa-devel@alsa-project.org (subscribers-only)
L: linux-omap@vger.kernel.org
@ -5117,6 +5118,11 @@ F: drivers/i2c/busses/i2c-pca-*
F: include/linux/i2c-algo-pca.h
F: include/linux/i2c-pca-platform.h
PCDP - PRIMARY CONSOLE AND DEBUG PORT
M: Khalid Aziz <khalid.aziz@hp.com>
S: Maintained
F: drivers/firmware/pcdp.*
PCI ERROR RECOVERY
M: Linas Vepstas <linasvepstas@gmail.com>
L: linux-pci@vger.kernel.org
@ -6466,6 +6472,7 @@ S: Odd Fixes
F: drivers/staging/olpc_dcon/
STAGING - OZMO DEVICES USB OVER WIFI DRIVER
M: Rupesh Gujare <rgujare@ozmodevices.com>
M: Chris Kelly <ckelly@ozmodevices.com>
S: Maintained
F: drivers/staging/ozwpan/
@ -7461,8 +7468,7 @@ F: include/linux/wm97xx.h
WOLFSON MICROELECTRONICS DRIVERS
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Ian Lartey <ian@opensource.wolfsonmicro.com>
M: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
L: patches@opensource.wolfsonmicro.com
T: git git://opensource.wolfsonmicro.com/linux-2.6-asoc
T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
@ -7573,8 +7579,8 @@ F: Documentation/filesystems/xfs.txt
F: fs/xfs/
XILINX AXI ETHERNET DRIVER
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
M: Anirudha Sarangi <anirudh@xilinx.com>
M: John Linn <John.Linn@xilinx.com>
S: Maintained
F: drivers/net/ethernet/xilinx/xilinx_axienet*

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 4
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc5
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*

68
arch/alpha/include/asm/atomic.h
View File

@ -3,6 +3,7 @@
#include <linux/types.h>
#include <asm/barrier.h>
#include <asm/cmpxchg.h>
/*
* Atomic operations that C can't guarantee us. Useful for
@ -168,73 +169,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
return result;
}
/*
* Atomic exchange routines.
*/
#define __ASM__MB
#define ____xchg(type, args...) __xchg ## type ## _local(args)
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
#include <asm/xchg.h>
#define xchg_local(ptr,x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
sizeof(*(ptr))); \
})
#define cmpxchg_local(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
(unsigned long)_n_, \
sizeof(*(ptr))); \
})
#define cmpxchg64_local(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg_local((ptr), (o), (n)); \
})
#ifdef CONFIG_SMP
#undef __ASM__MB
#define __ASM__MB "\tmb\n"
#endif
#undef ____xchg
#undef ____cmpxchg
#define ____xchg(type, args...) __xchg ##type(args)
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
#include <asm/xchg.h>
#define xchg(ptr,x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
sizeof(*(ptr))); \
})
#define cmpxchg(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr)));\
})
#define cmpxchg64(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg((ptr), (o), (n)); \
})
#undef __ASM__MB
#undef ____cmpxchg
#define __HAVE_ARCH_CMPXCHG 1
#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))

71
arch/alpha/include/asm/cmpxchg.h Normal file
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@ -0,0 +1,71 @@
#ifndef _ALPHA_CMPXCHG_H
#define _ALPHA_CMPXCHG_H
/*
* Atomic exchange routines.
*/
#define __ASM__MB
#define ____xchg(type, args...) __xchg ## type ## _local(args)
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
#include <asm/xchg.h>
#define xchg_local(ptr, x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
sizeof(*(ptr))); \
})
#define cmpxchg_local(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
(unsigned long)_n_, \
sizeof(*(ptr))); \
})
#define cmpxchg64_local(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg_local((ptr), (o), (n)); \
})
#ifdef CONFIG_SMP
#undef __ASM__MB
#define __ASM__MB "\tmb\n"
#endif
#undef ____xchg
#undef ____cmpxchg
#define ____xchg(type, args...) __xchg ##type(args)
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
#include <asm/xchg.h>
#define xchg(ptr, x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
sizeof(*(ptr))); \
})
#define cmpxchg(ptr, o, n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr)));\
})
#define cmpxchg64(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg((ptr), (o), (n)); \
})
#undef __ASM__MB
#undef ____cmpxchg
#define __HAVE_ARCH_CMPXCHG 1
#endif /* _ALPHA_CMPXCHG_H */

4
arch/alpha/include/asm/xchg.h
View File

@ -1,10 +1,10 @@
#ifndef _ALPHA_ATOMIC_H
#ifndef _ALPHA_CMPXCHG_H
#error Do not include xchg.h directly!
#else
/*
* xchg/xchg_local and cmpxchg/cmpxchg_local share the same code
* except that local version do not have the expensive memory barrier.
* So this file is included twice from asm/system.h.
* So this file is included twice from asm/cmpxchg.h.
*/
/*

2
arch/arm/boot/compressed/atags_to_fdt.c
View File

@ -77,6 +77,8 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
} else if (atag->hdr.tag == ATAG_MEM) {
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
continue;
mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
} else if (atag->hdr.tag == ATAG_INITRD2) {

2
arch/arm/boot/compressed/head.S
View File

@ -273,7 +273,7 @@ restart: adr r0, LC0
add r0, r0, #0x100
mov r1, r6
sub r2, sp, r6
blne atags_to_fdt
bleq atags_to_fdt
ldmfd sp!, {r0-r3, ip, lr}
sub sp, sp, #0x10000

1
arch/arm/boot/dts/at91sam9g20.dtsi
View File

@ -55,7 +55,6 @@
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};

1
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -56,7 +56,6 @@
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};

1
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -54,7 +54,6 @@
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};

1
arch/arm/boot/dts/db8500.dtsi
View File

@ -24,7 +24,6 @@
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
interrupt-parent;
reg = <0xa0411000 0x1000>,
<0xa0410100 0x100>;
};

1
arch/arm/boot/dts/highbank.dts
View File

@ -89,7 +89,6 @@
#size-cells = <0>;
#address-cells = <1>;
interrupt-controller;
interrupt-parent;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};

4
arch/arm/boot/dts/msm8660-surf.dts
View File

@ -10,7 +10,7 @@
intc: interrupt-controller@02080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <3>;
reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >;
};
@ -19,6 +19,6 @@
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
interrupts = <0 195 0x0>;
};
};

9
arch/arm/common/vic.c
View File

@ -427,19 +427,18 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
/*
* Handle each interrupt in a single VIC. Returns non-zero if we've
* handled at least one interrupt. This does a single read of the
* status register and handles all interrupts in order from LSB first.
* handled at least one interrupt. This reads the status register
* before handling each interrupt, which is necessary given that
* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
*/
static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
{
u32 stat, irq;
int handled = 0;
stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
while (stat) {
while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
irq = ffs(stat) - 1;
handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
stat &= ~(1 << irq);
handled = 1;
}

1
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_FB=y

2
arch/arm/configs/mini2440_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_ARCH_S3C24XX=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_S3C_ADC=y
CONFIG_S3C24XX_PWM=y
CONFIG_MACH_MINI2440=y

9
arch/arm/configs/u8500_defconfig
View File

@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB5500=y
CONFIG_UX500_SOC_DB8500=y
CONFIG_MACH_HREFV60=y
CONFIG_MACH_SNOWBALL=y
CONFIG_MACH_U5500=y
@ -39,7 +37,6 @@ CONFIG_CAIF=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_MISC_DEVICES=y
CONFIG_AB8500_PWM=y
CONFIG_SENSORS_BH1780=y
CONFIG_NETDEVICES=y
@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_I2C=y
CONFIG_I2C_NOMADIK=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TC3589X=y
CONFIG_POWER_SUPPLY=y
CONFIG_AB8500_BM=y
CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_TC3589X=y
CONFIG_AB5500_CORE=y
CONFIG_AB8500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AB8500=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_GADGET=y

2
arch/arm/include/asm/jump_label.h
View File

@ -14,7 +14,7 @@
#define JUMP_LABEL_NOP "nop"
#endif
static __always_inline bool arch_static_branch(struct jump_label_key *key)
static __always_inline bool arch_static_branch(struct static_key *key)
{
asm goto("1:\n\t"
JUMP_LABEL_NOP "\n\t"

16
arch/arm/kernel/setup.c
View File

@ -523,7 +523,21 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
*/
size -= start & ~PAGE_MASK;
bank->start = PAGE_ALIGN(start);
bank->size = size & PAGE_MASK;
#ifndef CONFIG_LPAE
if (bank->start + size < bank->start) {
printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
"32-bit physical address space\n", (long long)start);
/*
* To ensure bank->start + bank->size is representable in
* 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
* This means we lose a page after masking.
*/
size = ULONG_MAX - bank->start;
}
#endif
bank->size = size & PAGE_MASK;
/*
* Check whether this memory region has non-zero size or

1
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}

2
arch/arm/mach-at91/at91rm9200_time.c
View File

@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <asm/mach/time.h>
@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
};
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
void __init at91rm9200_ioremap_st(u32 addr)
{

2
arch/arm/mach-at91/board-rm9200ek.c
View File

@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
};
#define EK_FLASH_BASE AT91_CHIPSELECT_0
#define EK_FLASH_SIZE SZ_2M
#define EK_FLASH_SIZE SZ_8M
static struct physmap_flash_data ek_flash_data = {
.width = 2,

5
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = {
.flags = IORESOURCE_MEM
},
[2] = {
.start = AT91_PIN_PC11,
.end = AT91_PIN_PC11,
.flags = IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
}
@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
static void __init ek_add_device_dm9000(void)
{
struct resource *r = &dm9000_resource[2];
/* Configure chip-select 2 (DM9000) */
sam9_smc_configure(0, 2, &dm9000_smc_config);
@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void)
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
platform_device_register(&dm9000_device);
}
#else

1
arch/arm/mach-at91/clock.c
View File

@ -35,6 +35,7 @@
#include "generic.h"
void __iomem *at91_pmc_base;
EXPORT_SYMBOL_GPL(at91_pmc_base);
/*
* There's a lot more which can be done with clocks, including cpufreq

2
arch/arm/mach-at91/include/mach/at91_pmc.h
View File

@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
#define at91_pmc_write(field, value) \
__raw_writel(value, at91_pmc_base + field)
#else
.extern at91_aic_base
.extern at91_pmc_base
#endif
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */

2
arch/arm/mach-at91/setup.c
View File

@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
}
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
}
void __iomem *at91_matrix_base;
EXPORT_SYMBOL_GPL(at91_matrix_base);
void __init at91_ioremap_matrix(u32 base_addr)
{

4
arch/arm/mach-bcmring/core.c
View File

@ -52,8 +52,8 @@
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>
static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
static struct clk pll1_clk = {
.name = "PLL1",

2
arch/arm/mach-exynos/Kconfig
View File

@ -368,6 +368,7 @@ comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT
bool "Samsung Exynos4 Machine using device tree"
depends on ARCH_EXYNOS4
select CPU_EXYNOS4210
select USE_OF
select ARM_AMBA
@ -380,6 +381,7 @@ config MACH_EXYNOS4_DT
config MACH_EXYNOS5_DT
bool "SAMSUNG EXYNOS5 Machine using device tree"
depends on ARCH_EXYNOS5
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA

24
arch/arm/mach-exynos/clock-exynos4.c
View File

@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

24
arch/arm/mach-exynos/clock-exynos5.c
View File

@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit = (1 << 20),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15),
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

14
arch/arm/mach-exynos/common.c
View File

@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
{
int irq;
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

13
arch/arm/mach-exynos/dev-dwmci.c
View File

@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
};
static struct dw_mci_board exynos4_dwci_pdata = {

2
arch/arm/mach-exynos/include/mach/irqs.h
View File

@ -212,6 +212,8 @@
#define IRQ_MFC EXYNOS4_IRQ_MFC
#define IRQ_SDO EXYNOS4_IRQ_SDO
#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
#define IRQ_ADC EXYNOS4_IRQ_ADC0
#define IRQ_TC EXYNOS4_IRQ_PEN0

4
arch/arm/mach-exynos/include/mach/map.h
View File

@ -89,6 +89,10 @@
#define EXYNOS4_PA_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
#define EXYNOS5_PA_MDMA0 0x10800000
#define EXYNOS5_PA_MDMA1 0x11C10000
#define EXYNOS5_PA_PDMA0 0x121A0000
#define EXYNOS5_PA_PDMA1 0x121B0000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000

6
arch/arm/mach-exynos/include/mach/regs-clock.h
View File

@ -255,9 +255,15 @@
/* For EXYNOS5250 */
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)

2
arch/arm/mach-exynos/mach-exynos5-dt.c
View File

@ -45,7 +45,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
{},
};

47
arch/arm/mach-exynos/mach-nuri.c
View File

@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_ERASE),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
@ -307,49 +308,7 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
};
/* TSP */
static u8 mxt_init_vals[] = {
/* MXT_GEN_COMMAND(6) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_GEN_POWER(7) */
0x20, 0xff, 0x32,
/* MXT_GEN_ACQUIRE(8) */
0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
/* MXT_TOUCH_MULTI(9) */
0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00,
/* MXT_TOUCH_KEYARRAY(15) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
0x00,
/* MXT_SPT_GPIOPWM(19) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_GRIPFACE(20) */
0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
0x0f, 0x0a,
/* MXT_PROCG_NOISE(22) */
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
/* MXT_TOUCH_PROXIMITY(23) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_ONETOUCH(24) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_SPT_SELFTEST(25) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
/* MXT_PROCI_TWOTOUCH(27) */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* MXT_SPT_CTECONFIG(28) */
0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
};
static struct mxt_platform_data mxt_platform_data = {
.config = mxt_init_vals,
.config_length = ARRAY_SIZE(mxt_init_vals),
.x_line = 18,
.y_line = 11,
.x_size = 1024,
@ -571,7 +530,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = {
static struct regulator_init_data __initdata max8997_ldo8_data = {
.constraints = {
.name = "VUSB/VDAC_3.3V_C210",
.name = "VUSB+VDAC_3.3V_C210",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
@ -1347,6 +1306,7 @@ static struct platform_device *nuri_devices[] __initdata = {
static void __init nuri_map_io(void)
{
clk_xusbxti.rate = 24000000;
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
@ -1379,7 +1339,6 @@ static void __init nuri_machine_init(void)
nuri_camera_init();
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));

3
arch/arm/mach-exynos/mach-universal_c210.c
View File

@ -29,6 +29,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
@ -746,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
@ -1057,6 +1059,7 @@ static struct platform_device *universal_devices[] __initdata = {
static void __init universal_map_io(void)
{
clk_xusbxti.rate = 24000000;
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));

6
arch/arm/mach-imx/imx27-dt.c
View File

@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
static int __init imx27_avic_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
irq_domain_add_simple(np, 0);
irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
return 0;
}
@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
irq_domain_add_simple(np, gpio_irq_base);
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
NULL);
return 0;
}

2
arch/arm/mach-imx/mm-imx5.c
View File

@ -35,7 +35,7 @@ static void imx5_idle(void)
}
clk_enable(gpc_dvfs_clk);
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (tzic_enable_wake() != 0)
if (!tzic_enable_wake())
cpu_do_idle();
clk_disable(gpc_dvfs_clk);
}

3
arch/arm/mach-msm/board-halibut.c
View File

@ -86,9 +86,6 @@ static void __init halibut_init(void)
static void __init halibut_fixup(struct tag *tags, char **cmdline,
struct meminfo *mi)
{
mi->nr_banks=1;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].size = (101*1024*1024);
}
static void __init halibut_map_io(void)

25
arch/arm/mach-msm/board-msm8x60.c
View File

@ -17,6 +17,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
msm_map_msm8x60_io();
}
#ifdef CONFIG_OF
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
{}
};
#endif
static void __init msm8x60_init_irq(void)
{
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
if (!of_have_populated_dt())
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
#ifdef CONFIG_OF
else
of_irq_init(msm_dt_gic_match);
#endif
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
{}
};
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", },
{}
};
static void __init msm8x60_dt_init(void)
{
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
GIC_SPI_START);
if (of_machine_is_compatible("qcom,msm8660-surf")) {
printk(KERN_INFO "Init surf UART registers\n");
msm8x60_init_uart12dm();

1
arch/arm/mach-msm/board-trout-panel.c
View File

@ -12,6 +12,7 @@
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/system_info.h>
#include <mach/msm_fb.h>
#include <mach/vreg.h>

1
arch/arm/mach-msm/board-trout.c
View File

@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/clkdev.h>
#include <asm/system_info.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

2
arch/arm/mach-msm/proc_comm.c
View File

@ -121,7 +121,7 @@ int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
* and unknown state. This function should be called early to
* wait on the ARM9.
*/
void __init proc_comm_boot_wait(void)
void __devinit proc_comm_boot_wait(void)
{
void __iomem *base = MSM_SHARED_RAM_BASE;

1
arch/arm/mach-omap1/mux.c
View File

@ -27,6 +27,7 @@
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/hardware.h>
#include <plat/mux.h>

4
arch/arm/mach-omap1/timer.c
View File

@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
int n = (pdev->id - 1) << 1;
u32 l;
l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
l |= source << n;
__raw_writel(l, MOD_CONF_CTRL_1);
omap_writel(l, MOD_CONF_CTRL_1);
return 0;
}

12
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -20,6 +20,7 @@
#include <linux/usb/otg.h>
#include <linux/spi/spi.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/twl6040.h>
#include <linux/gpio_keys.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = {
},
};
static struct twl4030_codec_data twl6040_codec = {
static struct twl6040_codec_data twl6040_codec = {
/* single-step ramp for headset and handsfree */
.hs_left_step = 0x0f,
.hs_right_step = 0x0f,
@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = {
.hf_right_step = 0x1d,
};
static struct twl4030_vibra_data twl6040_vibra = {
static struct twl6040_vibra_data twl6040_vibra = {
.vibldrv_res = 8,
.vibrdrv_res = 3,
.viblmotor_res = 10,
@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = {
.vddvibr_uV = 0, /* fixed volt supply - VBAT */
};
static struct twl4030_audio_data twl6040_audio = {
static struct twl6040_platform_data twl6040_data = {
.codec = &twl6040_codec,
.vibra = &twl6040_vibra,
.audpwron_gpio = 127,
.naudint_irq = OMAP44XX_IRQ_SYS_2N,
.irq_base = TWL6040_CODEC_IRQ_BASE,
};
static struct twl4030_platform_data sdp4430_twldata = {
.audio = &twl6040_audio,
/* Regulators */
.vusim = &sdp4430_vusim,
.vaux1 = &sdp4430_vaux1,
@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void)
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &sdp4430_twldata);
omap4_pmic_init("twl6030", &sdp4430_twldata,
&twl6040_data, OMAP44XX_IRQ_SYS_2N);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
ARRAY_SIZE(sdp4430_i2c_3_boardinfo));

2
arch/arm/mach-omap2/board-generic.c
View File

@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
static void __init omap4_i2c_init(void)
{
omap4_pmic_init("twl6030", &sdp4430_twldata);
omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
}
static void __init omap4_init(void)

13
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -25,6 +25,7 @@
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/i2c/twl.h>
#include <linux/mfd/twl6040.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/wl12xx.h>
@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
return 0;
}
static struct twl4030_codec_data twl6040_codec = {
static struct twl6040_codec_data twl6040_codec = {
/* single-step ramp for headset and handsfree */
.hs_left_step = 0x0f,
.hs_right_step = 0x0f,
@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = {
.hf_right_step = 0x1d,
};
static struct twl4030_audio_data twl6040_audio = {
static struct twl6040_platform_data twl6040_data = {
.codec = &twl6040_codec,
.audpwron_gpio = 127,
.naudint_irq = OMAP44XX_IRQ_SYS_2N,
.irq_base = TWL6040_CODEC_IRQ_BASE,
};
/* Panda board uses the common PMIC configuration */
static struct twl4030_platform_data omap4_panda_twldata = {
.audio = &twl6040_audio,
};
static struct twl4030_platform_data omap4_panda_twldata;
/*
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void)
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &omap4_panda_twldata);
omap4_pmic_init("twl6030", &omap4_panda_twldata,
&twl6040_data, OMAP44XX_IRQ_SYS_2N);
omap_register_i2c_bus(2, 400, NULL, 0);
/*
* Bus 3 is attached to the DVI port where devices like the pico DLP

80
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@ -165,83 +165,3 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
return 0;
}
#ifdef CONFIG_CPU_FREQ
/*
* Walk PRCM rate table and fillout cpufreq freq_table
* XXX This should be replaced by an OPP layer in the near future
*/
static struct cpufreq_frequency_table *freq_table;
void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
{
const struct prcm_config *prcm;
int i = 0;
int tbl_sz = 0;
if (!cpu_is_omap24xx())
return;
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sclk->rate)
continue;
/* don't put bypass rates in table */
if (prcm->dpll_speed == prcm->xtal_speed)
continue;
tbl_sz++;
}
/*
* XXX Ensure that we're doing what CPUFreq expects for this error
* case and the following one
*/
if (tbl_sz == 0) {
pr_warning("%s: no matching entries in rate_table\n",
__func__);
return;
}
/* Include the CPUFREQ_TABLE_END terminator entry */
tbl_sz++;
freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
GFP_ATOMIC);
if (!freq_table) {
pr_err("%s: could not kzalloc frequency table\n", __func__);
return;
}
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sclk->rate)
continue;
/* don't put bypass rates in table */
if (prcm->dpll_speed == prcm->xtal_speed)
continue;
freq_table[i].index = i;
freq_table[i].frequency = prcm->mpu_speed / 1000;
i++;
}
freq_table[i].index = i;
freq_table[i].frequency = CPUFREQ_TABLE_END;
*table = &freq_table[0];
}
void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
{
if (!cpu_is_omap24xx())
return;
kfree(freq_table);
}
#endif

5
arch/arm/mach-omap2/clock.c
View File

@ -536,10 +536,5 @@ struct clk_functions omap2_clk_functions = {
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
.clk_disable_unused = omap2_clk_disable_unused,
#ifdef CONFIG_CPU_FREQ
/* These will be removed when the OPP code is integrated */
.clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
.clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
#endif
};

8
arch/arm/mach-omap2/clock.h
View File

@ -146,14 +146,6 @@ extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#else
#define omap2_clk_init_cpufreq_table 0
#define omap2_clk_exit_cpufreq_table 0
#endif
extern const struct clkops clkops_omap2_iclk_dflt_wait;
extern const struct clkops clkops_omap2_iclk_dflt;
extern const struct clkops clkops_omap2_iclk_idle_only;

17
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
goto dis_opt_clks;
_write_sysconfig(v, oh);
if (oh->class->sysc->srst_udelay)
udelay(oh->class->sysc->srst_udelay);
if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
omap_test_timeout((omap_hwmod_read(oh,
oh->class->sysc->syss_offs)
@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
*/
int omap_hwmod_softreset(struct omap_hwmod *oh)
{
if (!oh)
u32 v;
int ret;
if (!oh || !(oh->_sysc_cache))
return -EINVAL;
return _ocp_softreset(oh);
v = oh->_sysc_cache;
ret = _set_softreset(oh, &v);
if (ret)
goto error;
_write_sysconfig(v, oh);
error:
return ret;
}
/**

1
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
.flags = OMAP_FIREWALL_L4,
}
},
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

1
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
.slave = &omap2430_dss_venc_hwmod,
.clk = "dss_ick",
.addr = omap2_dss_venc_addrs,
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

1
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.flags = OMAP_FIREWALL_L4,
}
},
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};

9
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
/*
* ISS needs 100 OCP clk cycles delay after a softreset before
* accessing sysconfig again.
* The lowest frequency at the moment for L3 bus is 100 MHz, so
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
*
* TODO: Indicate errata when available.
*/
.srst_udelay = 2,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

124
arch/arm/mach-omap2/serial.c
View File

@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
static void omap_uart_set_smartidle(struct platform_device *pdev)
{
struct omap_device *od = to_omap_device(pdev);
u8 idlemode;
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
}
#else
@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
#endif /* CONFIG_PM */
#ifdef CONFIG_OMAP_MUX
static struct omap_device_pad default_uart1_pads[] __initdata = {
{
.name = "uart1_cts.uart1_cts",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart1_rts.uart1_rts",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart1_tx.uart1_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart1_rx.uart1_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_uart2_pads[] __initdata = {
{
.name = "uart2_cts.uart2_cts",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart2_rts.uart2_rts",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart2_tx.uart2_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart2_rx.uart2_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_uart3_pads[] __initdata = {
{
.name = "uart3_cts_rctx.uart3_cts_rctx",
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
},
{
.name = "uart3_rts_sd.uart3_rts_sd",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart3_tx_irtx.uart3_tx_irtx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart3_rx_irrx.uart3_rx_irrx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
},
};
static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
{
.name = "gpmc_wait2.uart4_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "gpmc_wait3.uart4_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
},
};
static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
{
.name = "uart4_tx.uart4_tx",
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
},
{
.name = "uart4_rx.uart4_rx",
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
},
};
static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
{
switch (bdata->id) {
case 0:
bdata->pads = default_uart1_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
break;
case 1:
bdata->pads = default_uart2_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
break;
case 2:
bdata->pads = default_uart3_pads;
bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
break;
case 3:
if (cpu_is_omap44xx()) {
bdata->pads = default_omap4_uart4_pads;
bdata->pads_cnt =
ARRAY_SIZE(default_omap4_uart4_pads);
} else if (cpu_is_omap3630()) {
bdata->pads = default_omap36xx_uart4_pads;
bdata->pads_cnt =
ARRAY_SIZE(default_omap36xx_uart4_pads);
}
break;
default:
break;
}
}
#else
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}

37
arch/arm/mach-omap2/twl-common.c
View File

@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
.flags = I2C_CLIENT_WAKE,
};
static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
{
.addr = 0x48,
.flags = I2C_CLIENT_WAKE,
},
{
I2C_BOARD_INFO("twl6040", 0x4b),
},
};
void __init omap_pmic_init(int bus, u32 clkrate,
const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data)
@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate,
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
}
void __init omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct twl6040_platform_data *twl6040_data, int twl6040_irq)
{
/* PMIC part*/
strncpy(omap4_i2c1_board_info[0].type, pmic_type,
sizeof(omap4_i2c1_board_info[0].type));
omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
omap4_i2c1_board_info[0].platform_data = pmic_data;
/* TWL6040 audio IC part */
omap4_i2c1_board_info[1].irq = twl6040_irq;
omap4_i2c1_board_info[1].platform_data = twl6040_data;
omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
}
void __init omap_pmic_late_init(void)
{
/* Init the OMAP TWL parameters (if PMIC has been registerd) */
if (!pmic_i2c_board_info.irq)
return;
omap3_twl_init();
omap4_twl_init();
if (pmic_i2c_board_info.irq)
omap3_twl_init();
if (omap4_i2c1_board_info[0].irq)
omap4_twl_init();
}
#if defined(CONFIG_ARCH_OMAP3)

10
arch/arm/mach-omap2/twl-common.h
View File

@ -29,6 +29,7 @@
struct twl4030_platform_data;
struct twl6040_platform_data;
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data);
@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type,
omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
}
static inline void omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
}
void omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data,
struct twl6040_platform_data *audio_data, int twl6040_irq);
void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
u32 pdata_flags, u32 regulators_flags);

7
arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
View File

@ -17,6 +17,7 @@
*
* bit 23 - Input/Output (PXA2xx specific)
* bit 24 - Wakeup Enable(PXA2xx specific)
* bit 25 - Keep Output (PXA2xx specific)
*/
#define MFP_DIR_IN (0x0 << 23)
@ -25,6 +26,12 @@
#define MFP_DIR(x) (((x) >> 23) & 0x1)
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
/*
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
* retain their last output level (low or high).
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
*/
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)

21
arch/arm/mach-pxa/mfp-pxa2xx.c
View File

@ -33,6 +33,8 @@
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
#define PWER_WE35 (1 << 24)
@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
#ifdef CONFIG_PM
static unsigned long saved_gafr[2][4];
static unsigned long saved_gpdr[4];
static unsigned long saved_gplr[4];
static unsigned long saved_pgsr[4];
static int pxa2xx_mfp_suspend(void)
@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
}
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
saved_gafr[0][i] = GAFR_L(i);
saved_gafr[1][i] = GAFR_U(i);
saved_gpdr[i] = GPDR(i * 32);
saved_gplr[i] = GPLR(i * 32);
saved_pgsr[i] = PGSR(i);
GPDR(i * 32) = gpdr_lpm[i];
GPSR(i * 32) = PGSR(i);
GPCR(i * 32) = ~PGSR(i);
}
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
for (i = 0; i < pxa_last_gpio; i++) {
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
GPDR(i) |= GPIO_bit(i);
else
GPDR(i) &= ~GPIO_bit(i);
}
return 0;
}
@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
GAFR_L(i) = saved_gafr[0][i];
GAFR_U(i) = saved_gafr[1][i];
GPSR(i * 32) = saved_gplr[i];
GPCR(i * 32) = ~saved_gplr[i];
GPDR(i * 32) = saved_gpdr[i];
PGSR(i) = saved_pgsr[i];
}

6
arch/arm/mach-pxa/pxa27x.c
View File

@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
pxa_register_device(&pxa27x_device_i2c_power, info);
}
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
.gpio_set_wake = gpio_set_wake,
};
static struct platform_device *devices[] __initdata = {
&pxa_device_gpio,
&pxa27x_device_udc,
&pxa_device_pmu,
&pxa_device_i2s,
@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
}

8
arch/arm/mach-s3c24xx/Kconfig
View File

@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
help
Compile in platform device definition for Samsung TouchScreen.
# cpu-specific sections
if CPU_S3C2410
config S3C2410_DMA
bool
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@ -127,6 +123,10 @@ config S3C2410_PM
help
Power Management code common to S3C2410 and better
# cpu-specific sections
if CPU_S3C2410
config S3C24XX_SIMTEC_NOR
bool
help

2
arch/arm/mach-s5pv210/dma.c
View File

@ -33,8 +33,6 @@
#include <mach/irqs.h>
#include <mach/dma.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static u8 pdma0_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,

4
arch/arm/mach-s5pv210/mach-aquila.c
View File

@ -484,8 +484,8 @@ static struct wm8994_pdata wm8994_platform_data = {
.gpio_defaults[8] = 0x0100,
.gpio_defaults[9] = 0x0100,
.gpio_defaults[10] = 0x0100,
.ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
.ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, &wm8994_ldo2_data },
};
/* GPIO I2C PMIC */

6
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -25,6 +25,7 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/interrupt.h>
#include <asm/hardware/vic.h>
@ -674,8 +675,8 @@ static struct wm8994_pdata wm8994_platform_data = {
.gpio_defaults[8] = 0x0100,
.gpio_defaults[9] = 0x0100,
.gpio_defaults[10] = 0x0100,
.ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, NULL, &wm8994_ldo2_data },
.ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
.ldo[1] = { 0, &wm8994_ldo2_data },
};
/* GPIO I2C PMIC */
@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
/* MoviNAND */
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
.max_width = 4,
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
};

2
arch/arm/mach-sa1100/generic.c
View File

@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
}
static struct resource sa1100_rtc_resources[] = {
DEFINE_RES_MEM(0x90010000, 0x9001003f),
DEFINE_RES_MEM(0x90010000, 0x40),
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
};

6
arch/arm/mach-u300/core.c
View File

@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
for (i = 0; i < U300_VIC_IRQS_END; i++)
set_bit(i, (unsigned long *) &mask[0]);
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
mask[1], mask[1]);
}

9
arch/arm/mach-u300/i2c.c
View File

@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1,
.boot_on = 1,
},
@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 2500000,
.max_uV = 2500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1,
.boot_on = 1,
},
@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
},

150
arch/arm/mach-u300/include/mach/irqs.h
View File

@ -12,101 +12,101 @@
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_U300_INTCON0_START 0
#define IRQ_U300_INTCON1_START 32
#define IRQ_U300_INTCON0_START 1
#define IRQ_U300_INTCON1_START 33
/* These are on INTCON0 - 30 lines */
#define IRQ_U300_IRQ0_EXT 0
#define IRQ_U300_IRQ1_EXT 1
#define IRQ_U300_DMA 2
#define IRQ_U300_VIDEO_ENC_0 3
#define IRQ_U300_VIDEO_ENC_1 4
#define IRQ_U300_AAIF_RX 5
#define IRQ_U300_AAIF_TX 6
#define IRQ_U300_AAIF_VGPIO 7
#define IRQ_U300_AAIF_WAKEUP 8
#define IRQ_U300_PCM_I2S0_FRAME 9
#define IRQ_U300_PCM_I2S0_FIFO 10
#define IRQ_U300_PCM_I2S1_FRAME 11
#define IRQ_U300_PCM_I2S1_FIFO 12
#define IRQ_U300_XGAM_GAMCON 13
#define IRQ_U300_XGAM_CDI 14
#define IRQ_U300_XGAM_CDICON 15
#define IRQ_U300_IRQ0_EXT 1
#define IRQ_U300_IRQ1_EXT 2
#define IRQ_U300_DMA 3
#define IRQ_U300_VIDEO_ENC_0 4
#define IRQ_U300_VIDEO_ENC_1 5
#define IRQ_U300_AAIF_RX 6
#define IRQ_U300_AAIF_TX 7
#define IRQ_U300_AAIF_VGPIO 8
#define IRQ_U300_AAIF_WAKEUP 9
#define IRQ_U300_PCM_I2S0_FRAME 10
#define IRQ_U300_PCM_I2S0_FIFO 11
#define IRQ_U300_PCM_I2S1_FRAME 12
#define IRQ_U300_PCM_I2S1_FIFO 13
#define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 16
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
/* MMIACC not used on the DB3210 or DB3350 chips */
#define IRQ_U300_XGAM_MMIACC 16
#define IRQ_U300_XGAM_MMIACC 17
#endif
#define IRQ_U300_XGAM_PDI 17
#define IRQ_U300_XGAM_PDICON 18
#define IRQ_U300_XGAM_GAMEACC 19
#define IRQ_U300_XGAM_MCIDCT 20
#define IRQ_U300_APEX 21
#define IRQ_U300_UART0 22
#define IRQ_U300_SPI 23
#define IRQ_U300_TIMER_APP_OS 24
#define IRQ_U300_TIMER_APP_DD 25
#define IRQ_U300_TIMER_APP_GP1 26
#define IRQ_U300_TIMER_APP_GP2 27
#define IRQ_U300_TIMER_OS 28
#define IRQ_U300_TIMER_MS 29
#define IRQ_U300_KEYPAD_KEYBF 30
#define IRQ_U300_KEYPAD_KEYBR 31
#define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 20
#define IRQ_U300_XGAM_MCIDCT 21
#define IRQ_U300_APEX 22
#define IRQ_U300_UART0 23
#define IRQ_U300_SPI 24
#define IRQ_U300_TIMER_APP_OS 25
#define IRQ_U300_TIMER_APP_DD 26
#define IRQ_U300_TIMER_APP_GP1 27
#define IRQ_U300_TIMER_APP_GP2 28
#define IRQ_U300_TIMER_OS 29
#define IRQ_U300_TIMER_MS 30
#define IRQ_U300_KEYPAD_KEYBF 31
#define IRQ_U300_KEYPAD_KEYBR 32
/* These are on INTCON1 - 32 lines */
#define IRQ_U300_GPIO_PORT0 32
#define IRQ_U300_GPIO_PORT1 33
#define IRQ_U300_GPIO_PORT2 34
#define IRQ_U300_GPIO_PORT0 33
#define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 35
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 35
#define IRQ_U300_EVHIST 36
#define IRQ_U300_MSPRO 37
#define IRQ_U300_MMCSD_MCIINTR0 38
#define IRQ_U300_MMCSD_MCIINTR1 39
#define IRQ_U300_I2C0 40
#define IRQ_U300_I2C1 41
#define IRQ_U300_RTC 42
#define IRQ_U300_NFIF 43
#define IRQ_U300_NFIF2 44
#define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 37
#define IRQ_U300_MSPRO 38
#define IRQ_U300_MMCSD_MCIINTR0 39
#define IRQ_U300_MMCSD_MCIINTR1 40
#define IRQ_U300_I2C0 41
#define IRQ_U300_I2C1 42
#define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 45
#endif
/* DB3150 and DB3200 have only 45 IRQs */
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
#define U300_VIC_IRQS_END 45
#define U300_VIC_IRQS_END 46
#endif
/* The DB3350-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 45
#define IRQ_U300_ISP_F1 46
#define IRQ_U300_ISP_F2 47
#define IRQ_U300_ISP_F3 48
#define IRQ_U300_ISP_F4 49
#define IRQ_U300_GPIO_PORT3 50
#define IRQ_U300_SYSCON_PLL_LOCK 51
#define IRQ_U300_UART1 52
#define IRQ_U300_GPIO_PORT4 53
#define IRQ_U300_GPIO_PORT5 54
#define IRQ_U300_GPIO_PORT6 55
#define U300_VIC_IRQS_END 56
#define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 48
#define IRQ_U300_ISP_F3 49
#define IRQ_U300_ISP_F4 50
#define IRQ_U300_GPIO_PORT3 51
#define IRQ_U300_SYSCON_PLL_LOCK 52
#define IRQ_U300_UART1 53
#define IRQ_U300_GPIO_PORT4 54
#define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 57
#endif
/* The DB3210-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS365
#define IRQ_U300_GPIO_PORT3 35
#define IRQ_U300_GPIO_PORT4 36
#define IRQ_U300_WDOG 37
#define IRQ_U300_EVHIST 38
#define IRQ_U300_MSPRO 39
#define IRQ_U300_MMCSD_MCIINTR0 40
#define IRQ_U300_MMCSD_MCIINTR1 41
#define IRQ_U300_I2C0 42
#define IRQ_U300_I2C1 43
#define IRQ_U300_RTC 44
#define IRQ_U300_NFIF 45
#define IRQ_U300_NFIF2 46
#define IRQ_U300_SYSCON_PLL_LOCK 47
#define U300_VIC_IRQS_END 48
#define IRQ_U300_GPIO_PORT3 36
#define IRQ_U300_GPIO_PORT4 37
#define IRQ_U300_WDOG 38
#define IRQ_U300_EVHIST 39
#define IRQ_U300_MSPRO 40
#define IRQ_U300_MMCSD_MCIINTR0 41
#define IRQ_U300_MMCSD_MCIINTR1 42
#define IRQ_U300_I2C0 43
#define IRQ_U300_I2C1 44
#define IRQ_U300_RTC 45
#define IRQ_U300_NFIF 46
#define IRQ_U300_NFIF2 47
#define IRQ_U300_SYSCON_PLL_LOCK 48
#define U300_VIC_IRQS_END 49
#endif
/* Maximum 8*7 GPIO lines */
@ -117,6 +117,6 @@
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
#endif
#define NR_IRQS (IRQ_U300_GPIO_END)
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
#endif

1
arch/arm/mach-ux500/Kconfig
View File

@ -17,6 +17,7 @@ config UX500_SOC_DB5500
config UX500_SOC_DB8500
bool
select MFD_DB8500_PRCMU
select REGULATOR
select REGULATOR_DB8500_PRCMU
select CPU_FREQ_TABLE if CPU_FREQ

2
arch/arm/mach-ux500/mbox-db5500.c
View File

@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
return sprintf(buf, "0x%X\n", mbox_value);
}
static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
static int mbox_show(struct seq_file *s, void *data)
{

2
arch/arm/mach-ux500/platsmp.c
View File

@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(cpu_logical_map(cpu));
gic_raise_softirq(cpumask_of(cpu), 1);
smp_send_reschedule(cpu);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {

2
arch/arm/mm/Kconfig
View File

@ -723,7 +723,7 @@ config CPU_HIGH_VECTOR
bool "Select the High exception vector"
help
Say Y here to select high exception vector(0xFFFF0000~).
The exception vector can be vary depending on the platform
The exception vector can vary depending on the platform
design in nommu mode. If your platform needs to select
high exception vector, say Y.
Otherwise or if you are unsure, say N, and the low exception

2
arch/arm/mm/fault.c
View File

@ -320,7 +320,7 @@ retry:
*/
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
if (flags & FAULT_FLAG_ALLOW_RETRY) {
if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) {
if (fault & VM_FAULT_MAJOR) {
tsk->maj_flt++;
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,

2
arch/arm/mm/nommu.c
View File

@ -13,6 +13,7 @@
#include <asm/sections.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/traps.h>
#include <asm/mach/arch.h>
#include "mm.h"
@ -39,6 +40,7 @@ void __init sanity_check_meminfo(void)
*/
void __init paging_init(struct machine_desc *mdesc)
{
early_trap_init((void *)CONFIG_VECTORS_BASE);
bootmem_init();
}

12
arch/arm/mm/proc-v7.S
View File

@ -254,6 +254,18 @@ __v7_setup:
ldr r6, =NMRR @ NMRR
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
#endif
#ifndef CONFIG_ARM_THUMBEE
mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
and r0, r0, #(0xf << 12) @ ThumbEE enabled field
teq r0, #(1 << 12) @ check if ThumbEE is present
bne 1f
mov r5, #0
mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
mrc p14, 6, r0, c0, c0, 0 @ load TEECR
orr r0, r0, #1 @ set the 1st bit in order to
mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
1:
#endif
adr r5, v7_crval
ldmia r5, {r5, r6}

26
arch/arm/plat-omap/clock.c
View File

@ -398,32 +398,6 @@ struct clk dummy_ck = {
.ops = &clkops_null,
};
#ifdef CONFIG_CPU_FREQ
void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
{
unsigned long flags;
if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
return;
spin_lock_irqsave(&clockfw_lock, flags);
arch_clock->clk_init_cpufreq_table(table);
spin_unlock_irqrestore(&clockfw_lock, flags);
}
void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
{
unsigned long flags;
if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
return;
spin_lock_irqsave(&clockfw_lock, flags);
arch_clock->clk_exit_cpufreq_table(table);
spin_unlock_irqrestore(&clockfw_lock, flags);
}
#endif
/*
*
*/

10
arch/arm/plat-omap/include/plat/clock.h
View File

@ -272,8 +272,6 @@ struct clk {
#endif
};
struct cpufreq_frequency_table;
struct clk_functions {
int (*clk_enable)(struct clk *clk);
void (*clk_disable)(struct clk *clk);
@ -283,10 +281,6 @@ struct clk_functions {
void (*clk_allow_idle)(struct clk *clk);
void (*clk_deny_idle)(struct clk *clk);
void (*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};
extern int mpurate;
@ -301,10 +295,6 @@ extern void recalculate_root_clocks(void);
extern unsigned long followparent_recalc(struct clk *clk);
extern void clk_enable_init_clocks(void);
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#endif
extern struct clk *omap_clk_get_by_name(const char *name);
extern int omap_clk_enable_autoidle_all(void);
extern int omap_clk_disable_autoidle_all(void);

4
arch/arm/plat-omap/include/plat/omap_hwmod.h
View File

@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
* @rev_offs: IP block revision register offset (from module base addr)
* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
* @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
* @srst_udelay: Delay needed after doing a softreset in usecs
* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
* @clockact: the default value of the module CLOCKACTIVITY bits
@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
u16 sysc_offs;
u16 syss_offs;
u16 sysc_flags;
struct omap_hwmod_sysc_fields *sysc_fields;
u8 srst_udelay;
u8 idlemodes;
u8 clockact;
struct omap_hwmod_sysc_fields *sysc_fields;
};
/**

12
arch/arm/plat-omap/sram.c
View File

@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
}
#ifdef CONFIG_PM
void omap3_sram_restore_context(void)
{
omap_sram_ceil = omap_sram_base + omap_sram_size;
@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
omap3_sram_configure_core_dpll_sz);
omap_push_sram_idle();
}
#endif /* CONFIG_PM */
#endif /* CONFIG_ARCH_OMAP3 */
static inline int omap34xx_sram_init(void)
{
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
omap3_sram_restore_context();
#endif
return 0;
}
#else
static inline int omap34xx_sram_init(void)
{
return 0;
}
#endif /* CONFIG_ARCH_OMAP3 */
static inline int am33xx_sram_init(void)
{

1
arch/arm/plat-samsung/Kconfig
View File

@ -302,6 +302,7 @@ comment "Power management"
config SAMSUNG_PM_DEBUG
bool "S3C2410 PM Suspend debug"
depends on PM
select DEBUG_LL
help
Say Y here if you want verbose debugging from the PM Suspend and
Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>

28
arch/arm/plat-samsung/include/plat/sdhci.h
View File

@ -18,6 +18,8 @@
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
#include <plat/devs.h>
struct platform_device;
struct mmc_host;
struct mmc_card;
@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
static inline void s3c_sdhci_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S3C_DEV_HSMMC
case 0:
s3c_device_hsmmc0.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC1
case 1:
s3c_device_hsmmc1.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC2
case 2:
s3c_device_hsmmc2.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC3
case 3:
s3c_device_hsmmc3.name = name;
break;
#endif
}
}
#endif /* __PLAT_S3C_SDHCI_H */

53
arch/blackfin/mach-bf538/boards/ezkit.c
View File

@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#endif /* CONFIG_RTC_DRV_BFIN */
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
#ifdef CONFIG_SERIAL_BFIN_UART0
@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_UART0 */
#ifdef CONFIG_SERIAL_BFIN_UART1
static struct resource bfin_uart1_resources[] = {
{
@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_UART1 */
#ifdef CONFIG_SERIAL_BFIN_UART2
static struct resource bfin_uart2_resources[] = {
{
@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
},
};
#endif
#endif
#endif /* CONFIG_SERIAL_BFIN_UART2 */
#endif /* CONFIG_SERIAL_BFIN */
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
.resource = bfin_sir0_resources,
};
#endif
#endif /* CONFIG_BFIN_SIR0 */
#ifdef CONFIG_BFIN_SIR1
static struct resource bfin_sir1_resources[] = {
{
@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
.resource = bfin_sir1_resources,
};
#endif
#endif /* CONFIG_BFIN_SIR1 */
#ifdef CONFIG_BFIN_SIR2
static struct resource bfin_sir2_resources[] = {
{
@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
.resource = bfin_sir2_resources,
};
#endif
#endif
#endif /* CONFIG_BFIN_SIR2 */
#endif /* CONFIG_BFIN_SIR */
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
static struct resource bfin_sport1_uart_resources[] = {
{
@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
static struct resource bfin_sport2_uart_resources[] = {
{
@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
static struct resource bfin_sport3_uart_resources[] = {
{
@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
},
};
#endif
#endif
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
#endif /* CONFIG_SERIAL_BFIN_SPORT */
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
static unsigned short bfin_can_peripherals[] = {
@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
.platform_data = &bfin_can_peripherals, /* Passed to driver */
},
};
#endif
#endif /* CONFIG_CAN_BFIN */
/*
* USB-LAN EzExtender board
@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
.platform_data = &smc91x_info,
},
};
#endif
#endif /* CONFIG_SMC91X */
#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
/* all SPI peripherals info goes here */
@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
static struct bfin5xx_spi_chip spi_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
};
#endif
#endif /* CONFIG_MTD_M25P80 */
#endif /* CONFIG_SPI_BFIN5XX */
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
#include <linux/spi/ad7879.h>
@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
.gpio_export = 1, /* Export GPIO to gpiolib */
.gpio_base = -1, /* Dynamic allocation */
};
#endif
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
#include <asm/bfin-lq035q1.h>
@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
.platform_data = &bfin_lq035q1_data,
},
};
#endif
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
static struct spi_board_info bf538_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
},
#endif
#endif /* CONFIG_MTD_M25P80 */
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
{
.modalias = "ad7879",
@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.chip_select = 1,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
{
.modalias = "bfin-lq035q1-spi",
@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.chip_select = 2,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
.bus_num = 0,
.chip_select = 1,
},
#endif
#endif /* CONFIG_SPI_SPIDEV */
};
/* SPI (0) */
@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
},
};
#endif /* spi master and devices */
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
.resource = bfin_twi1_resource,
};
#endif
#endif
#endif /* CONFIG_BF542 */
#endif /* CONFIG_I2C_BLACKFIN_TWI */
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/gpio_keys.h>

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