Blackfin: unify cache init functions
The CPLB implementations (mpu/nompu) had exact copies of the cacheinit code. Even the i/d cache functions are largely the same. So unify them both in the common kernel cache code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
e78feaaeeb
commit
ea426e6c62
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@ -2,7 +2,7 @@
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# arch/blackfin/kernel/cplb-nompu/Makefile
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#
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obj-y := cplbinit.o cacheinit.o cplbmgr.o
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obj-y := cplbinit.o cplbmgr.o
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CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
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-ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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@ -1,71 +0,0 @@
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/*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#if defined(CONFIG_BFIN_ICACHE)
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void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
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bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
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}
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ctrl = bfin_read_IMEM_CONTROL();
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ctrl |= IMC | ENICPLB;
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_IMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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#if defined(CONFIG_BFIN_DCACHE)
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void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
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bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
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}
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ctrl = bfin_read_DMEM_CONTROL();
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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@ -2,7 +2,7 @@
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# arch/blackfin/kernel/cplb-nompu/Makefile
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#
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obj-y := cplbinit.o cacheinit.o cplbmgr.o
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obj-y := cplbinit.o cplbmgr.o
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CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
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-ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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@ -1,71 +0,0 @@
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/*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#if defined(CONFIG_BFIN_ICACHE)
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void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
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bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
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}
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ctrl = bfin_read_IMEM_CONTROL();
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ctrl |= IMC | ENICPLB;
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_IMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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#if defined(CONFIG_BFIN_DCACHE)
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void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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unsigned long ctrl;
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
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bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
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}
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ctrl = bfin_read_DMEM_CONTROL();
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
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/* CSYNC to ensure load store ordering */
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CSYNC();
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bfin_write_DMEM_CONTROL(ctrl);
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SSYNC();
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}
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#endif
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@ -1,14 +1,16 @@
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/*
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* Blackfin cache control code (simpler control-style functions)
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*
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* Copyright 2004-2008 Analog Devices Inc.
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/cplbinit.h>
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/* Invalidate the Entire Data cache by
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* clearing DMC[1:0] bits
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@ -34,3 +36,43 @@ void blackfin_invalidate_entire_icache(void)
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SSYNC();
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}
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#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
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static void
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bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
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unsigned long cplb_data, unsigned long mem_control,
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unsigned long mem_mask)
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{
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int i;
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for (i = 0; i < MAX_CPLBS; i++) {
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bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
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bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
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}
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_enable_cplb(mem_control, mem_mask);
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}
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#ifdef CONFIG_BFIN_ICACHE
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void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
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{
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bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
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(IMC | ENICPLB));
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}
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#endif
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#ifdef CONFIG_BFIN_DCACHE
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void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
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{
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/*
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* Anomaly notes:
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* 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
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* register, so that the port preferences for DAG0 and DAG1 are set
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* to port B
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*/
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bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
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(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
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}
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#endif
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#endif
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