ath5k: Update reset code
* Update reset and sync with HALs * Clean up eeprom settings and tweaking of initvals and put them on separate functions * Set/Restore 32KHz ref clk operation * Add some more documentation TODO: Spur mitigation, tpc, half/quarter rate, compression etc v2: Address comments from Bob and Felix and fix RSSI threshold bug introduced on the first version of the patch Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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a406c13909
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e8f055f0c3
6 changed files with 734 additions and 298 deletions
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@ -222,6 +222,7 @@
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#endif
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/* Initial values */
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#define AR5K_INIT_CYCRSSI_THR1 2
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#define AR5K_INIT_TX_LATENCY 502
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#define AR5K_INIT_USEC 39
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#define AR5K_INIT_USEC_TURBO 79
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@ -313,7 +314,7 @@ struct ath5k_srev_name {
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#define AR5K_SREV_AR5424 0x90 /* Condor */
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#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
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#define AR5K_SREV_AR5414 0xa0 /* Eagle */
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#define AR5K_SREV_AR2415 0xb0 /* Cobra */
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#define AR5K_SREV_AR2415 0xb0 /* Talon */
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#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
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#define AR5K_SREV_AR5418 0xca /* PCI-E */
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#define AR5K_SREV_AR2425 0xe0 /* Swan */
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@ -331,7 +332,7 @@ struct ath5k_srev_name {
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#define AR5K_SREV_RAD_2112B 0x46
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#define AR5K_SREV_RAD_2413 0x50
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#define AR5K_SREV_RAD_5413 0x60
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#define AR5K_SREV_RAD_2316 0x70
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#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
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#define AR5K_SREV_RAD_2317 0x80
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#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
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#define AR5K_SREV_RAD_2425 0xa2
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@ -340,7 +341,7 @@ struct ath5k_srev_name {
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#define AR5K_SREV_PHY_5211 0x30
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#define AR5K_SREV_PHY_5212 0x41
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#define AR5K_SREV_PHY_5212A 0x42
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#define AR5K_SREV_PHY_2112B 0x43
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#define AR5K_SREV_PHY_5212B 0x43
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#define AR5K_SREV_PHY_2413 0x45
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#define AR5K_SREV_PHY_5413 0x61
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#define AR5K_SREV_PHY_2425 0x70
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@ -1030,7 +1031,6 @@ struct ath5k_hw {
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u16 ah_phy_revision;
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u16 ah_radio_5ghz_revision;
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u16 ah_radio_2ghz_revision;
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u32 ah_phy_spending;
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enum ath5k_version ah_version;
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enum ath5k_radio ah_radio;
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@ -1156,6 +1156,7 @@ extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_l
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/* EEPROM access functions */
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extern int ath5k_eeprom_init(struct ath5k_hw *ah);
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extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
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extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
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/* Protocol Control Unit Functions */
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extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
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@ -1258,6 +1259,7 @@ extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
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/*
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* Translate usec to hw clock units
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* TODO: Half/quarter rate
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*/
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static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
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{
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@ -1266,6 +1268,7 @@ static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
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/*
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* Translate hw clock units to usec
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* TODO: Half/quarter rate
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*/
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static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
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{
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@ -169,7 +169,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
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break;
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case AR5K_SREV_RAD_5112:
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case AR5K_SREV_RAD_2112:
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@ -177,38 +176,31 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
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break;
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case AR5K_SREV_RAD_2413:
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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break;
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case AR5K_SREV_RAD_5413:
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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break;
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case AR5K_SREV_RAD_2316:
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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break;
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case AR5K_SREV_RAD_2317:
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ah->ah_radio = AR5K_RF2317;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
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break;
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case AR5K_SREV_RAD_5424:
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if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
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ah->ah_mac_version == AR5K_SREV_AR2417){
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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}
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break;
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default:
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@ -227,29 +219,25 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else if (srev == AR5K_SREV_AR5213A &&
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ah->ah_phy_revision == AR5K_SREV_PHY_2112B) {
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ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
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ah->ah_radio = AR5K_RF5112;
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ah->ah_single_chip = false;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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} else {
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ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
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ret = -ENODEV;
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@ -204,7 +204,7 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
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/* Get antenna modes */
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ah->ah_antenna[mode][0] =
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(ee->ee_ant_control[mode][0] << 4) | 0x1;
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(ee->ee_ant_control[mode][0] << 4);
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ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
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ee->ee_ant_control[mode][1] |
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(ee->ee_ant_control[mode][2] << 6) |
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@ -1412,6 +1412,7 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
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return 0;
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}
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/*
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* Read the MAC address from eeprom
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*/
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return 0;
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}
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bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
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{
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u16 data;
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ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
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if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
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return true;
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else
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return false;
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}
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@ -25,6 +25,7 @@
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#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
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#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
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#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
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#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
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#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
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#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
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#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
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#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
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#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
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#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
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#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
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/*
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*/
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#define AR5K_DCU_SEQNUM_BASE 0x1140
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#define AR5K_DCU_SEQNUM_M 0x00000fff
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#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
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#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
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/*
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* DCU global IFS SIFS register
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#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */
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#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */
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#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */
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#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* Test ARM (Adaptive Radio Mode ?) */
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#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */
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/*
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* Default antenna register [5211+]
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* TSF parameter register
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*/
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#define AR5K_TSF_PARM 0x8104 /* Register Address */
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#define AR5K_TSF_PARM_INC_M 0x000000ff /* Mask for TSF increment */
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#define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */
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#define AR5K_TSF_PARM_INC_S 0
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/*
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#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
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#define AR5K_QOS_NOACK_BIT_OFFSET_S 4
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#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
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#define AR5K_QOS_NOACK_BYTE_OFFSET_S 8
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#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
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/*
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* PHY error filter register
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* TST_2 (Misc config parameters)
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*/
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#define AR5K_PHY_TST2 0x9800 /* Register Address */
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#define AR5K_PHY_TST2_TRIG_SEL 0x00000001 /* Trigger select (?) (field ?) */
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#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) (field ?) */
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#define AR5K_PHY_TST2_CBUS_MODE 0x00000100 /* Cardbus mode (?) */
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/* bit reserved */
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#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/
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#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */
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#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */
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#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */
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#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
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#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
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#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
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#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch) */
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#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
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#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
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#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */
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#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */
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#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
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#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
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#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* TX end to XLNA on */
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#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 0
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#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */
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#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
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#define AR5K_PHY_ADC_CTL 0x982c
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#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
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#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
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#define AR5K_PHY_SETTLING_AGC_S 0
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#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
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#define AR5K_PHY_SETTLINK_SWITCH_S 7
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#define AR5K_PHY_SETTLING_SWITCH_S 7
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/*
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* PHY Gain registers
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* PHY sleep registers [5112+]
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*/
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#define AR5K_PHY_SCR 0x9870
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#define AR5K_PHY_SCR_32MHZ 0x0000001f
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#define AR5K_PHY_SLMT 0x9874
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#define AR5K_PHY_SLMT_32MHZ 0x0000007f
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#define AR5K_PHY_SCAL 0x9878
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#define AR5K_PHY_SCAL_32MHZ 0x0000000e
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#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
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#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
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/*
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* PHY PLL (Phase Locked Loop) control register
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#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
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#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */
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#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */
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#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x00000010 /* Switch table idle (?) */
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#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */
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#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
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/*
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* PHY receiver delay register [5111+]
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#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
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#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
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#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
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#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 0
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#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
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#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
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#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
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#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
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AR5K_PHY_FRAME_CTL_PARITY_ERR | \
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AR5K_PHY_FRAME_CTL_TIMING_ERR
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/*
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* PHY Tx Power adjustment register [5212A+]
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*/
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#define AR5K_PHY_TX_PWR_ADJ 0x994c
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#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
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#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
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#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
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#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
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/*
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* PHY radar detection register [5111+]
|
||||
*/
|
||||
|
@ -2331,7 +2341,7 @@
|
|||
#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
|
||||
#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
|
||||
#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
|
||||
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ff3000
|
||||
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
|
||||
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
|
||||
|
||||
/*
|
||||
|
@ -2459,17 +2469,7 @@
|
|||
#define AR5K_PHY_SDELAY 0x99f4
|
||||
#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
|
||||
#define AR5K_PHY_SPENDING 0x99f8
|
||||
#define AR5K_PHY_SPENDING_14 0x00000014
|
||||
#define AR5K_PHY_SPENDING_18 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF5111 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF5112 0x00000014
|
||||
/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
|
||||
/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
|
||||
#define AR5K_PHY_SPENDING_RF5413 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF2413 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF2316 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF2317 0x00000018
|
||||
#define AR5K_PHY_SPENDING_RF2425 0x00000014
|
||||
|
||||
|
||||
/*
|
||||
* PHY PAPD I (power?) table (?)
|
||||
|
|
File diff suppressed because it is too large
Load diff
Reference in a new issue