sh: pci: New-style controller registration.
This moves off of the board_pci_channels[] approach for bus registration and over to a cleaner register_pci_controller(), all derived from the MIPS code. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
99f95f1178
commit
e79066a659
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@ -13,40 +13,90 @@
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#include <linux/init.h>
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#include <linux/dma-debug.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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/*
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* The PCI controller list.
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*/
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static struct pci_channel *hose_head, **hose_tail = &hose_head;
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static int pci_initialized;
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static void __devinit pcibios_scanbus(struct pci_channel *hose)
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{
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static int next_busno;
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struct pci_bus *bus;
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/* Catch botched conversion attempts */
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BUG_ON(hose->init);
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bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
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if (bus) {
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next_busno = bus->subordinate + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224)
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next_busno = 0;
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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pci_enable_bridges(bus);
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}
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}
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static DEFINE_MUTEX(pci_scan_mutex);
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void __devinit register_pci_controller(struct pci_channel *hose)
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{
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if (request_resource(&iomem_resource, hose->mem_resource) < 0)
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goto out;
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if (request_resource(&ioport_resource, hose->io_resource) < 0) {
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release_resource(hose->mem_resource);
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goto out;
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}
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*hose_tail = hose;
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hose_tail = &hose->next;
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/*
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* Do not panic here but later - this might hapen before console init.
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*/
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if (!hose->io_map_base) {
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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/*
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* Scan the bus if it is register after the PCI subsystem
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* initialization.
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*/
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if (pci_initialized) {
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mutex_lock(&pci_scan_mutex);
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pcibios_scanbus(hose);
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mutex_unlock(&pci_scan_mutex);
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}
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return;
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out:
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printk(KERN_WARNING
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"Skipping PCI bus scan due to resource conflict\n");
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}
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static int __init pcibios_init(void)
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{
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struct pci_channel *p;
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struct pci_bus *bus;
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int busno;
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struct pci_channel *hose;
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/* init channels */
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busno = 0;
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for (p = board_pci_channels; p->init; p++) {
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if (p->init(p) == 0)
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p->enabled = 1;
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else
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pr_err("Unable to init pci channel %d\n", busno);
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busno++;
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}
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/* scan the buses */
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busno = 0;
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for (p = board_pci_channels; p->init; p++) {
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if (p->enabled) {
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bus = pci_scan_bus(busno, p->pci_ops, p);
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busno = bus->subordinate + 1;
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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pci_enable_bridges(bus);
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}
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}
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/* Scan all of the recorded PCI controllers. */
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for (hose = hose_head; hose; hose = hose->next)
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pcibios_scanbus(hose);
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pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
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dma_debug_add_bus(&pci_bus_type);
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pci_initialized = 1;
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return 0;
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}
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subsys_initcall(pcibios_init);
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@ -74,7 +124,6 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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@ -186,5 +235,3 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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EXPORT_SYMBOL(board_pci_channels);
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@ -15,11 +15,47 @@
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#include <linux/delay.h>
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#include "pci-sh4.h"
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static int __init sh7780_pci_init(struct pci_channel *chan)
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extern u8 pci_cache_line_size;
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7785_mem_resource = {
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.name = "SH7785_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_channel sh7780_pci_controller = {
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.pci_ops = &sh4_pci_ops,
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.mem_resource = &sh7785_mem_resource,
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.io_resource = &sh7785_io_resource,
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};
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static struct sh4_pci_address_map sh7780_pci_map = {
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.window0 = {
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#if defined(CONFIG_32BIT)
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.base = SH7780_32BIT_DDR_BASE_ADDR,
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.size = 0x40000000,
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#else
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.base = SH7780_CS0_BASE_ADDR,
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.size = 0x20000000,
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#endif
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},
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};
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static int __init sh7780_pci_init(void)
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{
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struct pci_channel *chan = &sh7780_pci_controller;
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unsigned int id;
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const char *type = NULL;
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int ret;
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u32 word;
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printk(KERN_NOTICE "PCI: Starting intialization.\n");
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@ -54,52 +90,6 @@ static int __init sh7780_pci_init(struct pci_channel *chan)
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if ((ret = sh4_pci_check_direct(chan)) != 0)
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return ret;
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/*
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* Platform specific initialization (BSC registers, and memory space
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* mapping) will be called via the platform defined function
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* pcibios_init_platform().
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*/
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return pcibios_init_platform();
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}
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extern u8 pci_cache_line_size;
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static struct resource sh7785_io_resource = {
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.name = "SH7785_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7785_mem_resource = {
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.name = "SH7785_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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struct pci_channel board_pci_channels[] = {
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{ sh7780_pci_init, &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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static struct sh4_pci_address_map sh7780_pci_map = {
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.window0 = {
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#if defined(CONFIG_32BIT)
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.base = SH7780_32BIT_DDR_BASE_ADDR,
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.size = 0x40000000,
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#else
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.base = SH7780_CS0_BASE_ADDR,
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.size = 0x20000000,
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#endif
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},
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};
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int __init pcibios_init_platform(void)
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{
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struct pci_channel *chan = &board_pci_channels[0];
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u32 word;
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/*
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* Set the class and sub-class codes.
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*/
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@ -153,5 +143,8 @@ int __init pcibios_init_platform(void)
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__set_io_port_base(SH7780_PCI_IO_BASE);
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register_pci_controller(chan);
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return 0;
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}
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arch_initcall(sh7780_pci_init);
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@ -17,17 +17,22 @@
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* external) PCI controllers.
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*/
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struct pci_channel {
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int (*init)(struct pci_channel *chan);
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struct pci_ops *pci_ops;
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struct resource *io_resource;
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struct resource *mem_resource;
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int first_devfn;
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int last_devfn;
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int enabled;
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unsigned long reg_base;
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unsigned long io_base;
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struct pci_channel *next;
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unsigned long io_map_base;
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int (*init)(struct pci_channel *chan);
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struct pci_ops *pci_ops;
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struct resource *io_resource;
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struct resource *mem_resource;
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int first_devfn;
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int last_devfn;
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int enabled;
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unsigned long reg_base;
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unsigned long io_base;
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unsigned long io_map_base;
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};
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/*
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@ -35,6 +40,8 @@ struct pci_channel {
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*/
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extern struct pci_channel board_pci_channels[];
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extern void register_pci_controller(struct pci_channel *hose);
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extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
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struct pci_dev;
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