dect: coa: write BMC configuration when setting channel mode
Write the BMC configuration when setting the channel mode. This allows to reserve memory for only a single configuration for both RX and TX. Additionally it will in the future be used to configure S-field error parameters dynamically. Signed-off-by: Patrick McHardy <kaber@trash.net>
This commit is contained in:
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34b95935ff
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e783777ac8
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@ -63,8 +63,7 @@
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* 0x0e - 0x35: B-Field B-Field
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*
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* 0x3a - 0x3e: Radio Cfg Radio Cfg
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* 0x40 - 0x47: BMC TX Cfg
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* 0x48 - 0x4f: BMC RX Cfg
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* 0x40 - 0x47: BMC Ctrl BMC Ctrl
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* 0x50 - 0x5f: DCS IV/Key DCS IV/Key
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* 0x70 - 0x7b: DCS state DCS state
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*/
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@ -591,6 +590,42 @@ static void sc1442x_lock(const struct dect_transceiver *trx, u8 slot)
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sc1442x_unlock_mem(dev);
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}
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static void sc1442x_write_bmc_config(const struct coa_device *dev,
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u8 slot, bool tx)
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{
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u16 off;
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u8 cfg;
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off = sc1442x_slot_offset(slot) + BMC_CTRL;
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cfg = 2 << SC1442X_BC0_S_ERR_SHIFT;
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cfg |= SC1442X_BC0_INV_TDO;
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cfg |= SC1442X_BC0_SENS_A;
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if (slot < 12 && !tx)
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cfg |= SC1442X_BC0_PP_MODE;
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sc1442x_dwriteb(dev, off + 0, cfg);
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/* S-field error mask */
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sc1442x_dwriteb(dev, off + 1, 0);
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/* S-field sliding window error mask */
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sc1442x_dwriteb(dev, off + 2, 0x3f);
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/* DAC output */
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sc1442x_dwriteb(dev, off + 3, 0);
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cfg = SC1442X_BC4_ADP;
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cfg |= 0xf & SC1442X_BC4_WIN_MASK;
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cfg |= 0x80;
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sc1442x_dwriteb(dev, off + 4, cfg);
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cfg = SC1442X_BC5_DO_FR;
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cfg |= tx ? SC1442X_BC5_TDO_DIGITAL : SC1442X_BC5_TDO_POWER_DOWN;
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sc1442x_dwriteb(dev, off + 5, cfg);
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/* Frame number */
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sc1442x_dwriteb(dev, off + 6, 0);
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}
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static void sc1442x_set_mode(const struct dect_transceiver *trx,
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const struct dect_channel_desc *chd,
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enum dect_slot_states mode)
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@ -618,6 +653,9 @@ static void sc1442x_set_mode(const struct dect_transceiver *trx,
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
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sc1442x_rx_funcs[chd->pkt][chd->b_fmt][cipher][sync]);
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sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
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sc1442x_write_bmc_config(dev, slot, false);
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break;
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case DECT_SLOT_TX:
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sc1442x_write_cmd(dev, slottable[prev] + 0, BK_C,
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@ -626,6 +664,9 @@ static void sc1442x_set_mode(const struct dect_transceiver *trx,
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sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
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sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
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sc1442x_tx_funcs[chd->pkt][chd->b_fmt][cipher]);
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sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
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sc1442x_write_bmc_config(dev, slot, true);
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break;
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}
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sc1442x_unlock_mem(dev);
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@ -672,7 +713,7 @@ static void sc1442x_tx(const struct dect_transceiver *trx, struct sk_buff *skb)
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sc1442x_to_dmem(dev, off + SD_PREAMBLE_OFF,
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skb_mac_header(skb), skb->mac_len);
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sc1442x_to_dmem(dev, off + SD_DATA_OFF, skb->data, skb->len);
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sc1442x_dwriteb(dev, off + BMC_TX_CTRL + BMC_CTRL_MFR_OFF, cb->frame);
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sc1442x_dwriteb(dev, off + BMC_CTRL + BMC_CTRL_MFR_OFF, cb->frame);
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/* Init DCS for slots in the first half frame */
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if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
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@ -835,7 +876,7 @@ out:
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dect_transceiver_record_rssi(event, slot, rssi);
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/* Update frame number for next reception */
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sc1442x_dwriteb(dev, off + BMC_RX_CTRL + BMC_CTRL_MFR_OFF, framenum + 1);
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sc1442x_dwriteb(dev, off + BMC_CTRL + BMC_CTRL_MFR_OFF, framenum + 1);
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/* Init DCS for slots in the first half frame */
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if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
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@ -879,47 +920,12 @@ out:
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}
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EXPORT_SYMBOL_GPL(sc1442x_interrupt);
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static void sc1442x_write_bmc_config(const struct coa_device *dev,
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u16 off, bool pp, bool tx)
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{
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u8 cfg;
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cfg = 2 << SC1442X_BC0_S_ERR_SHIFT;
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cfg |= SC1442X_BC0_INV_TDO;
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cfg |= SC1442X_BC0_SENS_A;
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if (pp && !tx)
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cfg |= SC1442X_BC0_PP_MODE;
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sc1442x_dwriteb(dev, off + 0, cfg);
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/* S-field error mask */
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sc1442x_dwriteb(dev, off + 1, 0);
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/* S-field sliding window error mask */
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sc1442x_dwriteb(dev, off + 2, 0x3f);
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/* DAC output */
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sc1442x_dwriteb(dev, off + 3, 0);
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cfg = SC1442X_BC4_ADP;
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cfg |= 0xf & SC1442X_BC4_WIN_MASK;
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cfg |= 0x80;
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sc1442x_dwriteb(dev, off + 4, cfg);
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cfg = SC1442X_BC5_DO_FR;
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cfg |= tx ? SC1442X_BC5_TDO_DIGITAL : SC1442X_BC5_TDO_POWER_DOWN;
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sc1442x_dwriteb(dev, off + 5, cfg);
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/* Frame number */
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sc1442x_dwriteb(dev, off + 6, 0);
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}
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static void sc1442x_init_slot(const struct coa_device *dev, u8 slot)
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{
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u16 off;
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sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
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off = sc1442x_slot_offset(slot);
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sc1442x_write_bmc_config(dev, off + BMC_TX_CTRL, slot < 12, true);
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sc1442x_write_bmc_config(dev, off + BMC_RX_CTRL, slot < 12, false);
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dev->radio_ops->rx_init(dev, off);
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dev->radio_ops->tx_init(dev, off);
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}
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@ -987,7 +993,7 @@ int sc1442x_init_device(struct coa_device *dev)
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for (i = 1; i < SC1442X_CC_SIZE; i++)
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sc1442x_dwriteb(dev, DIP_CC_INIT + i, 0);
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sc1442x_write_bmc_config(dev, BMC_CTRL_INIT, false, false);
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sc1442x_write_bmc_config(dev, 0, false);
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for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
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sc1442x_init_slot(dev, slot);
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@ -34,8 +34,6 @@ BANK6_HIGH EQU 0xd0
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BANK7_LOW EQU 0xe0
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BANK7_HIGH EQU 0xf0
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BMC_CTRL_INIT EQU 0x00
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; Codec Control
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DIP_CC_INIT EQU 0x10
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@ -44,8 +42,7 @@ RF_DESC EQU 0x3a
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; BMC control information
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BMC_CTRL_SIZE EQU 7
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BMC_TX_CTRL EQU 0x40
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BMC_RX_CTRL EQU 0x48
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BMC_CTRL EQU 0x40
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; (multi) frame number for scambler and DCS
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BMC_CTRL_MFR_OFF EQU 6
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@ -225,7 +222,7 @@ label_58: B_RST
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; (93 bits total)
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;
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Receive: B_RST
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B_RC BMC_RX_CTRL
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B_RC BMC_CTRL
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WT BMC_CTRL_SIZE + 1
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P_LDH PB_RX_ON
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P_LDL PB_RSSI ; enable RSSI measurement
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@ -247,7 +244,7 @@ ClockSyncOff: P_SC 0x00 ; | p: 30 S: 46
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RTN ; Return | p: 93 A: 61
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ReceiveSync: B_RST
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B_RC BMC_RX_CTRL
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B_RC BMC_CTRL
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WT BMC_CTRL_SIZE + 1
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P_LDH PB_RX_ON
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P_LDL PB_RSSI ; enable RSSI measurement
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@ -285,7 +282,7 @@ ReceiveEnd: P_LDH PB_RSSI ; |
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Transmit: P_LDH 0x00 ;
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WT 40 ;
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B_RST ;
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B_RC BMC_TX_CTRL ;
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B_RC BMC_CTRL ;
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WNT 1 ; Wait until beginning of slot
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B_ST 0x00 ; Start transmission of S-field data |
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WT 1 ; Wait one bit | p: -8 S: 0
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@ -411,7 +408,7 @@ InitDIP: ;B_RST
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BK_C BANK0_LOW
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C_LD DIP_CC_INIT
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WT 10
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B_RC BMC_CTRL_INIT
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B_RC BMC_CTRL
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WT BMC_CTRL_SIZE + 1
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B_RST
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;C_ON
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@ -424,7 +421,7 @@ RFStart: BR SyncInit
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;-------------------------------------------------------------
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SHARED DIP_CC_INIT,RF_DESC
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SHARED BMC_CTRL_INIT,BMC_RX_CTRL,BMC_TX_CTRL,BMC_CTRL_MFR_OFF
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SHARED BMC_CTRL,BMC_CTRL_MFR_OFF
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SHARED SD_RSSI_OFF,SD_CSUM_OFF,SD_PREAMBLE_OFF,SD_DATA_OFF
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SHARED SlotTable
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@ -33,13 +33,13 @@ const unsigned char sc1442x_firmware[] = {
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0x02, 0xa8, 0x01, 0x67, 0x39, 0x00, 0x09, 0x06,
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0x20, 0x00, 0xec, 0x50, 0x09, 0x05, 0x08, 0x01,
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0x04, 0x00, 0x39, 0x00, 0x09, 0x06, 0x20, 0x00,
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0xec, 0x50, 0x04, 0x00, 0x20, 0x00, 0x33, 0x48,
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0xec, 0x50, 0x04, 0x00, 0x20, 0x00, 0x33, 0x40,
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0x09, 0x08, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
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0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
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0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
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0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
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0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x20, 0x00,
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0x33, 0x48, 0x09, 0x08, 0xed, 0x40, 0xec, 0x01,
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0x33, 0x40, 0x09, 0x08, 0xed, 0x40, 0xec, 0x01,
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0x09, 0x19, 0x08, 0x01, 0x09, 0x08, 0x27, 0x00,
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0xea, 0x20, 0xed, 0x02, 0x09, 0x05, 0x29, 0x00,
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0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02, 0x09, 0x20,
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@ -68,6 +68,6 @@ const unsigned char sc1442x_firmware[] = {
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0x03, 0xed, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
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0x01, 0xdf, 0x08, 0x17, 0xea, 0x00, 0x02, 0x38,
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0x61, 0x00, 0x08, 0x16, 0x01, 0xdf, 0x0f, 0x00,
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0xfa, 0x10, 0x09, 0x0a, 0x33, 0x00, 0x09, 0x08,
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0xfa, 0x10, 0x09, 0x0a, 0x33, 0x40, 0x09, 0x08,
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0x20, 0x00, 0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04,
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0x62, 0x00, 0x0b, 0x00, 0x01, 0xde};
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@ -5,9 +5,7 @@ extern const unsigned char sc1442x_firmware[510];
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#define DIP_CC_INIT 0x10
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#define RF_DESC 0x3A
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#define BMC_CTRL_INIT 0x0
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#define BMC_RX_CTRL 0x48
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#define BMC_TX_CTRL 0x40
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#define BMC_CTRL 0x40
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#define BMC_CTRL_MFR_OFF 0x6
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#define SD_RSSI_OFF 0x0
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#define SD_CSUM_OFF 0x1
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