ARM: Realview/Versatile/Integrator: remove unused definitions from platform.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
4ce1755275
commit
e606a940cb
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@ -23,9 +23,6 @@
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*
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* Integrator address map
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*
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* NOTE: This is a multi-hosted header file for use with uHAL and
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* supported debuggers.
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*
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* ***********************************************************************/
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#ifndef __address_h
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@ -330,20 +327,6 @@
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*/
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#define PHYS_PCI_V3_BASE 0x62000000
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#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
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/* 'export' these to UHAL */
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#define UHAL_PCI_IO PCI_IO_BASE
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#define UHAL_PCI_MEM PCI_MEM_BASE
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#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
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#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
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#define UHAL_PCI_MAX_SLOT 20
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/* ========================================================================
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* Start of uHAL definitions
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* ========================================================================
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*/
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/* ------------------------------------------------------------------------
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* Integrator Interrupt Controllers
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* ------------------------------------------------------------------------
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@ -391,7 +374,7 @@
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*/
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/* ------------------------------------------------------------------------
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* LED's - The header LED is not accessible via the uHAL API
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* LED's
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* ------------------------------------------------------------------------
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*
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*/
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@ -403,35 +386,19 @@
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#define LED_BANK INTEGRATOR_DBG_LEDS
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/*
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* Memory definitions - run uHAL out of SSRAM.
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*
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*/
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#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
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/*
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* Clean base - dummy
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*
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*/
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#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
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/*
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* Timer definitions
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*
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* Only use timer 1 & 2
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* (both run at 24MHz and will need the clock divider set to 16).
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*
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* Timer 0 runs at bus frequency and therefore could vary and currently
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* uHAL can't handle that.
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*
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* Timer 0 runs at bus frequency
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*/
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#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
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#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
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#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
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#define MAX_TIMER 2
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#define MAX_PERIOD 699050
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#define TICKS_PER_uSEC 24
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/*
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@ -439,14 +406,9 @@
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*
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*/
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#define mSEC_1 1000
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#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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#define mSEC_25 (mSEC_1 * 25)
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#define SEC_1 (mSEC_1 * 1000)
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#define INTEGRATOR_CSR_BASE 0x10000000
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#define INTEGRATOR_CSR_SIZE 0x10000000
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#endif
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/* END */
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@ -231,12 +231,6 @@
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#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
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#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
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/*
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* Clean base - dummy
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*
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*/
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#define CLEAN_BASE REALVIEW_BOOT_ROM_HI
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/*
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* System controller bit assignment
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*/
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@ -249,20 +243,6 @@
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#define REALVIEW_TIMER4_EnSel 21
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#define MAX_TIMER 2
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#define MAX_PERIOD 699050
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#define TICKS_PER_uSEC 1
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/*
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* These are useconds NOT ticks.
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*
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*/
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#define mSEC_1 1000
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#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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#define mSEC_25 (mSEC_1 * 25)
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#define SEC_1 (mSEC_1 * 1000)
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#define REALVIEW_CSR_BASE 0x10000000
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#define REALVIEW_CSR_SIZE 0x10000000
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@ -205,7 +205,7 @@
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#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
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#define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */
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#define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */
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#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
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#define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */
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/* 0x10000000 - 0x100FFFFF */
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#define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */
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#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
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@ -213,7 +213,7 @@
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#define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */
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#define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */
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#define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */
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#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
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#define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */
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#define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */
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#define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */
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#define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */
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@ -379,12 +379,6 @@
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#define SIC_INT_PCI3 30
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/*
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* Clean base - dummy
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*
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*/
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#define CLEAN_BASE VERSATILE_BOOT_ROM_HI
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/*
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* System controller bit assignment
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*/
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@ -397,20 +391,6 @@
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#define VERSATILE_TIMER4_EnSel 21
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#define MAX_TIMER 2
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#define MAX_PERIOD 699050
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#define TICKS_PER_uSEC 1
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/*
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* These are useconds NOT ticks.
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*
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*/
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#define mSEC_1 1000
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#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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#define mSEC_25 (mSEC_1 * 25)
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#define SEC_1 (mSEC_1 * 1000)
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#define VERSATILE_CSR_BASE 0x10000000
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#define VERSATILE_CSR_SIZE 0x10000000
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@ -432,5 +412,3 @@
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#endif
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#endif
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/* END */
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