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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 

Conflicts:
	net/mac80211/main.c
This commit is contained in:
David S. Miller 2010-09-09 22:27:33 -07:00
parent cbd9da7be8 053d8f6622
commit e548833df8
774 changed files with 11148 additions and 12678 deletions
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7
Documentation/DocBook/kernel-locking.tmpl
View File

@ -1922,9 +1922,12 @@ machines due to caching.
<function>mutex_lock()</function>
</para>
<para>
There is a <function>mutex_trylock()</function> which can be
used inside interrupt context, as it will not sleep.
There is a <function>mutex_trylock()</function> which does not
sleep. Still, it must not be used inside interrupt context since
its implementation is not safe for that.
<function>mutex_unlock()</function> will also never sleep.
It cannot be used in interrupt context either since a mutex
must be released by the same task that acquired it.
</para>
</listitem>
</itemizedlist>

5
Documentation/DocBook/tracepoint.tmpl
View File

@ -104,4 +104,9 @@
<title>Block IO</title>
!Iinclude/trace/events/block.h
</chapter>
<chapter id="workqueue">
<title>Workqueue</title>
!Iinclude/trace/events/workqueue.h
</chapter>
</book>

4
Documentation/hwmon/f71882fg
View File

@ -2,10 +2,6 @@ Kernel driver f71882fg
======================
Supported chips:
* Fintek F71808E
Prefix: 'f71808fg'
Addresses scanned: none, address read from Super I/O config space
Datasheet: Not public
* Fintek F71858FG
Prefix: 'f71858fg'
Addresses scanned: none, address read from Super I/O config space

23
Documentation/kernel-parameters.txt
View File

@ -1974,15 +1974,18 @@ and is between 256 and 4096 characters. It is defined in the file
force Enable ASPM even on devices that claim not to support it.
WARNING: Forcing ASPM on may cause system lockups.
pcie_ports= [PCIE] PCIe ports handling:
auto Ask the BIOS whether or not to use native PCIe services
associated with PCIe ports (PME, hot-plug, AER). Use
them only if that is allowed by the BIOS.
native Use native PCIe services associated with PCIe ports
unconditionally.
compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe
ports driver.
pcie_pme= [PCIE,PM] Native PCIe PME signaling options:
Format: {auto|force}[,nomsi]
auto Use native PCIe PME signaling if the BIOS allows the
kernel to control PCIe config registers of root ports.
force Use native PCIe PME signaling even if the BIOS refuses
to allow the kernel to control the relevant PCIe config
registers.
nomsi Do not use MSI for native PCIe PME signaling (this makes
all PCIe root ports use INTx for everything).
all PCIe root ports use INTx for all services).
pcmv= [HW,PCMCIA] BadgePAD 4
@ -2629,8 +2632,10 @@ and is between 256 and 4096 characters. It is defined in the file
aux-ide-disks -- unplug non-primary-master IDE devices
nics -- unplug network devices
all -- unplug all emulated devices (NICs and IDE disks)
ignore -- continue loading the Xen platform PCI driver even
if the version check failed
unnecessary -- unplugging emulated devices is
unnecessary even if the host did not respond to
the unplug protocol
never -- do not unplug even if version check succeeds
xirc2ps_cs= [NET,PCMCIA]
Format:

4
Documentation/laptops/thinkpad-acpi.txt
View File

@ -1024,6 +1024,10 @@ ThinkPad-specific interface. The driver will disable its native
backlight brightness control interface if it detects that the standard
ACPI interface is available in the ThinkPad.
If you want to use the thinkpad-acpi backlight brightness control
instead of the generic ACPI video backlight brightness control for some
reason, you should use the acpi_backlight=vendor kernel parameter.
The brightness_enable module parameter can be used to control whether
the LCD brightness control feature will be enabled when available.
brightness_enable=0 forces it to be disabled. brightness_enable=1

3
Documentation/lguest/Makefile
View File

@ -1,5 +1,6 @@
# This creates the demonstration utility "lguest" which runs a Linux guest.
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -I../../include -I../../arch/x86/include -U_FORTIFY_SOURCE
# Missing headers? Add "-I../../include -I../../arch/x86/include"
CFLAGS:=-m32 -Wall -Wmissing-declarations -Wmissing-prototypes -O3 -U_FORTIFY_SOURCE
all: lguest

23
Documentation/lguest/lguest.c
View File

@ -39,14 +39,14 @@
#include <limits.h>
#include <stddef.h>
#include <signal.h>
#include "linux/lguest_launcher.h"
#include "linux/virtio_config.h"
#include "linux/virtio_net.h"
#include "linux/virtio_blk.h"
#include "linux/virtio_console.h"
#include "linux/virtio_rng.h"
#include "linux/virtio_ring.h"
#include "asm/bootparam.h"
#include <linux/virtio_config.h>
#include <linux/virtio_net.h>
#include <linux/virtio_blk.h>
#include <linux/virtio_console.h>
#include <linux/virtio_rng.h>
#include <linux/virtio_ring.h>
#include <asm/bootparam.h>
#include "../../include/linux/lguest_launcher.h"
/*L:110
* We can ignore the 42 include files we need for this program, but I do want
* to draw attention to the use of kernel-style types.
@ -1447,14 +1447,15 @@ static void add_to_bridge(int fd, const char *if_name, const char *br_name)
static void configure_device(int fd, const char *tapif, u32 ipaddr)
{
struct ifreq ifr;
struct sockaddr_in *sin = (struct sockaddr_in *)&ifr.ifr_addr;
struct sockaddr_in sin;
memset(&ifr, 0, sizeof(ifr));
strcpy(ifr.ifr_name, tapif);
/* Don't read these incantations. Just cut & paste them like I did! */
sin->sin_family = AF_INET;
sin->sin_addr.s_addr = htonl(ipaddr);
sin.sin_family = AF_INET;
sin.sin_addr.s_addr = htonl(ipaddr);
memcpy(&ifr.ifr_addr, &sin, sizeof(sin));
if (ioctl(fd, SIOCSIFADDR, &ifr) != 0)
err(1, "Setting %s interface address", tapif);
ifr.ifr_flags = IFF_UP;

31
Documentation/powerpc/booting-without-of.txt
View File

@ -49,40 +49,13 @@ Table of Contents
f) MDIO on GPIOs
g) SPI busses
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
2) Child nodes of /system-controller
a) Marvell Discovery MDIO bus
b) Marvell Discovery ethernet controller
c) Marvell Discovery PHY nodes
d) Marvell Discovery SDMA nodes
e) Marvell Discovery BRG nodes
f) Marvell Discovery CUNIT nodes
g) Marvell Discovery MPSCROUTING nodes
h) Marvell Discovery MPSCINTR nodes
i) Marvell Discovery MPSC nodes
j) Marvell Discovery Watch Dog Timer nodes
k) Marvell Discovery I2C nodes
l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
n) Marvell Discovery GPP (General Purpose Pins) nodes
o) Marvell Discovery PCI host bridge node
p) Marvell Discovery CPU Error nodes
q) Marvell Discovery SRAM Controller nodes
r) Marvell Discovery PCI Error Handler nodes
s) Marvell Discovery Memory Controller nodes
VIII - Specifying interrupt information for devices
VII - Specifying interrupt information for devices
1) interrupts property
2) interrupt-parent property
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
IX - Specifying GPIO information for devices
1) gpios property
2) gpio-controller nodes
X - Specifying device power management information (sleep property)
VIII - Specifying device power management information (sleep property)
Appendix A - Sample SOC node for MPC8540

2
Documentation/powerpc/hvcs.txt
View File

@ -560,7 +560,7 @@ The proper channel for reporting bugs is either through the Linux OS
distribution company that provided your OS or by posting issues to the
PowerPC development mailing list at:
linuxppc-dev@ozlabs.org
linuxppc-dev@lists.ozlabs.org
This request is to provide a documented and searchable public exchange
of the problems and solutions surrounding this driver for the benefit of

99
MAINTAINERS
View File

@ -454,9 +454,20 @@ L: linux-rdma@vger.kernel.org
S: Maintained
F: drivers/infiniband/hw/amso1100/
ANALOG DEVICES INC ASOC DRIVERS
L: uclinux-dist-devel@blackfin.uclinux.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://blackfin.uclinux.org/
S: Supported
F: sound/soc/blackfin/*
F: sound/soc/codecs/ad1*
F: sound/soc/codecs/adau*
F: sound/soc/codecs/adav*
F: sound/soc/codecs/ssm*
AOA (Apple Onboard Audio) ALSA DRIVER
M: Johannes Berg <johannes@sipsolutions.net>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Maintained
F: sound/aoa/
@ -1441,6 +1452,16 @@ S: Maintained
F: Documentation/video4linux/cafe_ccic
F: drivers/media/video/cafe_ccic*
CAIF NETWORK LAYER
M: Sjur Braendeland <sjur.brandeland@stericsson.com>
L: netdev@vger.kernel.org
S: Supported
F: Documentation/networking/caif/
F: drivers/net/caif/
F: include/linux/caif/
F: include/net/caif/
F: net/caif/
CALGARY x86-64 IOMMU
M: Muli Ben-Yehuda <muli@il.ibm.com>
M: "Jon D. Mason" <jdmason@kudzu.us>
@ -1479,8 +1500,8 @@ F: include/linux/can/platform/
CELL BROADBAND ENGINE ARCHITECTURE
M: Arnd Bergmann <arnd@arndb.de>
L: linuxppc-dev@ozlabs.org
L: cbe-oss-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: cbe-oss-dev@lists.ozlabs.org
W: http://www.ibm.com/developerworks/power/cell/
S: Supported
F: arch/powerpc/include/asm/cell*.h
@ -1672,8 +1693,7 @@ F: kernel/cgroup*
F: mm/*cgroup*
CORETEMP HARDWARE MONITORING DRIVER
M: Rudolf Marek <r.marek@assembler.cz>
M: Huaxu Wan <huaxu.wan@intel.com>
M: Fenghua Yu <fenghua.yu@intel.com>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/coretemp
@ -2198,6 +2218,12 @@ L: linux-rdma@vger.kernel.org
S: Supported
F: drivers/infiniband/hw/ehca/
EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
M: Breno Leitao <leitao@linux.vnet.ibm.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ehea/
EMBEDDED LINUX
M: Paul Gortmaker <paul.gortmaker@windriver.com>
M: Matt Mackall <mpm@selenic.com>
@ -2293,6 +2319,12 @@ S: Maintained
F: Documentation/hwmon/f71805f
F: drivers/hwmon/f71805f.c
FANOTIFY
M: Eric Paris <eparis@redhat.com>
S: Maintained
F: fs/notify/fanotify/
F: include/linux/fanotify.h
FARSYNC SYNCHRONOUS DRIVER
M: Kevin Curtis <kevin.curtis@farsite.co.uk>
W: http://www.farsite.co.uk/
@ -2378,13 +2410,13 @@ F: include/linux/fb.h
FREESCALE DMA DRIVER
M: Li Yang <leoli@freescale.com>
M: Zhang Wei <zw@zh-kernel.org>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/dma/fsldma.*
FREESCALE I2C CPM DRIVER
M: Jochen Friedrich <jochen@scram.de>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/busses/i2c-cpm.c
@ -2400,7 +2432,7 @@ F: drivers/video/imxfb.c
FREESCALE SOC FS_ENET DRIVER
M: Pantelis Antoniou <pantelis.antoniou@gmail.com>
M: Vitaly Bordug <vbordug@ru.mvista.com>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/fs_enet/
@ -2408,7 +2440,7 @@ F: include/linux/fs_enet_pd.h
FREESCALE QUICC ENGINE LIBRARY
M: Timur Tabi <timur@freescale.com>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Supported
F: arch/powerpc/sysdev/qe_lib/
F: arch/powerpc/include/asm/*qe.h
@ -2416,27 +2448,27 @@ F: arch/powerpc/include/asm/*qe.h
FREESCALE USB PERIPHERAL DRIVERS
M: Li Yang <leoli@freescale.com>
L: linux-usb@vger.kernel.org
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/usb/gadget/fsl*
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
M: Li Yang <leoli@freescale.com>
L: netdev@vger.kernel.org
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/net/ucc_geth*
FREESCALE QUICC ENGINE UCC UART DRIVER
M: Timur Tabi <timur@freescale.com>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Supported
F: drivers/serial/ucc_uart.c
FREESCALE SOC SOUND DRIVERS
M: Timur Tabi <timur@freescale.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Supported
F: sound/soc/fsl/fsl*
F: sound/soc/fsl/mpc8610_hpcd.c
@ -2571,7 +2603,7 @@ F: mm/memory-failure.c
F: mm/hwpoison-inject.c
HYPERVISOR VIRTUAL CONSOLE DRIVER
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Odd Fixes
F: drivers/char/hvc_*
@ -3489,9 +3521,9 @@ F: drivers/usb/misc/legousbtower.c
LGUEST
M: Rusty Russell <rusty@rustcorp.com.au>
L: lguest@ozlabs.org
L: lguest@lists.ozlabs.org
W: http://lguest.ozlabs.org/
S: Maintained
S: Odd Fixes
F: Documentation/lguest/
F: arch/x86/lguest/
F: drivers/lguest/
@ -3508,7 +3540,7 @@ LINUX FOR POWERPC (32-BIT AND 64-BIT)
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
M: Paul Mackerras <paulus@samba.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
Q: http://patchwork.ozlabs.org/project/linuxppc-dev/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
S: Supported
@ -3518,14 +3550,14 @@ F: arch/powerpc/
LINUX FOR POWER MACINTOSH
M: Benjamin Herrenschmidt <benh@kernel.crashing.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/powermac/
F: drivers/macintosh/
LINUX FOR POWERPC EMBEDDED MPC5XXX
M: Grant Likely <grant.likely@secretlab.ca>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
T: git git://git.secretlab.ca/git/linux-2.6.git
S: Maintained
F: arch/powerpc/platforms/512x/
@ -3535,7 +3567,7 @@ LINUX FOR POWERPC EMBEDDED PPC4XX
M: Josh Boyer <jwboyer@linux.vnet.ibm.com>
M: Matt Porter <mporter@kernel.crashing.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
F: arch/powerpc/platforms/40x/
@ -3544,7 +3576,7 @@ F: arch/powerpc/platforms/44x/
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
M: Grant Likely <grant.likely@secretlab.ca>
W: http://wiki.secretlab.ca/index.php/Linux_on_Xilinx_Virtex
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
T: git git://git.secretlab.ca/git/linux-2.6.git
S: Maintained
F: arch/powerpc/*/*virtex*
@ -3554,20 +3586,20 @@ LINUX FOR POWERPC EMBEDDED PPC8XX
M: Vitaly Bordug <vitb@kernel.crashing.org>
M: Marcelo Tosatti <marcelo@kvack.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/8xx/
LINUX FOR POWERPC EMBEDDED PPC83XX AND PPC85XX
M: Kumar Gala <galak@kernel.crashing.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/83xx/
LINUX FOR POWERPC PA SEMI PWRFICIENT
M: Olof Johansson <olof@lixom.net>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/pasemi/
F: drivers/*/*pasemi*
@ -3920,8 +3952,7 @@ F: Documentation/sound/oss/MultiSound
F: sound/oss/msnd*
MULTITECH MULTIPORT CARD (ISICOM)
M: Jiri Slaby <jirislaby@gmail.com>
S: Maintained
S: Orphan
F: drivers/char/isicom.c
F: include/linux/isicom.h
@ -4600,7 +4631,7 @@ F: include/linux/preempt.h
PRISM54 WIRELESS DRIVER
M: "Luis R. Rodriguez" <mcgrof@gmail.com>
L: linux-wireless@vger.kernel.org
W: http://prism54.org
W: http://wireless.kernel.org/en/users/Drivers/p54
S: Obsolete
F: drivers/net/wireless/prism54/
@ -4613,14 +4644,14 @@ F: drivers/ata/sata_promise.*
PS3 NETWORK SUPPORT
M: Geoff Levand <geoff@infradead.org>
L: netdev@vger.kernel.org
L: cbe-oss-dev@ozlabs.org
L: cbe-oss-dev@lists.ozlabs.org
S: Maintained
F: drivers/net/ps3_gelic_net.*
PS3 PLATFORM SUPPORT
M: Geoff Levand <geoff@infradead.org>
L: linuxppc-dev@ozlabs.org
L: cbe-oss-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: cbe-oss-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/boot/ps3*
F: arch/powerpc/include/asm/lv1call.h
@ -4634,7 +4665,7 @@ F: sound/ppc/snd_ps3*
PS3VRAM DRIVER
M: Jim Paris <jim@jtan.com>
L: cbe-oss-dev@ozlabs.org
L: cbe-oss-dev@lists.ozlabs.org
S: Maintained
F: drivers/block/ps3vram.c
@ -5080,7 +5111,7 @@ F: drivers/mmc/host/sdhci.*
SECURE DIGITAL HOST CONTROLLER INTERFACE, OPEN FIRMWARE BINDINGS (SDHCI-OF)
M: Anton Vorontsov <avorontsov@ru.mvista.com>
L: linuxppc-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: linux-mmc@vger.kernel.org
S: Maintained
F: drivers/mmc/host/sdhci-of.*
@ -5497,8 +5528,8 @@ F: drivers/net/spider_net*
SPU FILE SYSTEM
M: Jeremy Kerr <jk@ozlabs.org>
L: linuxppc-dev@ozlabs.org
L: cbe-oss-dev@ozlabs.org
L: linuxppc-dev@lists.ozlabs.org
L: cbe-oss-dev@lists.ozlabs.org
W: http://www.ibm.com/developerworks/power/cell/
S: Supported
F: Documentation/filesystems/spufs.txt

6
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 36
EXTRAVERSION = -rc1
EXTRAVERSION = -rc3
NAME = Sheep on Meth
# *DOCUMENTATION*
@ -1408,8 +1408,8 @@ checkstack:
$(OBJDUMP) -d vmlinux $$(find . -name '*.ko') | \
$(PERL) $(src)/scripts/checkstack.pl $(CHECKSTACK_ARCH)
kernelrelease: include/config/kernel.release
@echo $(KERNELRELEASE)
kernelrelease:
@echo "$(KERNELVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
kernelversion:
@echo $(KERNELVERSION)

1
arch/alpha/include/asm/cache.h
View File

@ -17,7 +17,6 @@
# define L1_CACHE_SHIFT 5
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#endif

6
arch/alpha/kernel/err_marvel.c
View File

@ -109,7 +109,7 @@ marvel_print_err_cyc(u64 err_cyc)
#define IO7__ERR_CYC__CYCLE__M (0x7)
printk("%s Packet In Error: %s\n"
"%s Error in %s, cycle %ld%s%s\n",
"%s Error in %s, cycle %lld%s%s\n",
err_print_prefix,
packet_desc[EXTRACT(err_cyc, IO7__ERR_CYC__PACKET)],
err_print_prefix,
@ -313,7 +313,7 @@ marvel_print_po7_ugbge_sym(u64 ugbge_sym)
}
printk("%s Up Hose Garbage Symptom:\n"
"%s Source Port: %ld - Dest PID: %ld - OpCode: %s\n",
"%s Source Port: %lld - Dest PID: %lld - OpCode: %s\n",
err_print_prefix,
err_print_prefix,
EXTRACT(ugbge_sym, IO7__PO7_UGBGE_SYM__UPH_SRC_PORT),
@ -552,7 +552,7 @@ marvel_print_pox_spl_cmplt(u64 spl_cmplt)
#define IO7__POX_SPLCMPLT__REM_BYTE_COUNT__M (0xfff)
printk("%s Split Completion Error:\n"
"%s Source (Bus:Dev:Func): %ld:%ld:%ld\n",
"%s Source (Bus:Dev:Func): %lld:%lld:%lld\n",
err_print_prefix,
err_print_prefix,
EXTRACT(spl_cmplt, IO7__POX_SPLCMPLT__SOURCE_BUS),

2
arch/alpha/kernel/osf_sys.c
View File

@ -252,7 +252,7 @@ SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname,
retval = user_path(pathname, &path);
if (!retval) {
retval = do_osf_statfs(&path buffer, bufsiz);
retval = do_osf_statfs(&path, buffer, bufsiz);
path_put(&path);
}
return retval;

18
arch/alpha/kernel/perf_event.c
View File

@ -241,20 +241,20 @@ static inline unsigned long alpha_read_pmc(int idx)
static int alpha_perf_event_set_period(struct perf_event *event,
struct hw_perf_event *hwc, int idx)
{
long left = atomic64_read(&hwc->period_left);
long left = local64_read(&hwc->period_left);
long period = hwc->sample_period;
int ret = 0;
if (unlikely(left <= -period)) {
left = period;
atomic64_set(&hwc->period_left, left);
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
if (unlikely(left <= 0)) {
left += period;
atomic64_set(&hwc->period_left, left);
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
@ -269,7 +269,7 @@ static int alpha_perf_event_set_period(struct perf_event *event,
if (left > (long)alpha_pmu->pmc_max_period[idx])
left = alpha_pmu->pmc_max_period[idx];
atomic64_set(&hwc->prev_count, (unsigned long)(-left));
local64_set(&hwc->prev_count, (unsigned long)(-left));
alpha_write_pmc(idx, (unsigned long)(-left));
@ -300,10 +300,10 @@ static unsigned long alpha_perf_event_update(struct perf_event *event,
long delta;
again:
prev_raw_count = atomic64_read(&hwc->prev_count);
prev_raw_count = local64_read(&hwc->prev_count);
new_raw_count = alpha_read_pmc(idx);
if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
new_raw_count) != prev_raw_count)
goto again;
@ -316,8 +316,8 @@ again:
delta += alpha_pmu->pmc_max_period[idx] + 1;
}
atomic64_add(delta, &event->count);
atomic64_sub(delta, &hwc->period_left);
local64_add(delta, &event->count);
local64_sub(delta, &hwc->period_left);
return new_raw_count;
}
@ -636,7 +636,7 @@ static int __hw_perf_event_init(struct perf_event *event)
if (!hwc->sample_period) {
hwc->sample_period = alpha_pmu->pmc_max_period[0];
hwc->last_period = hwc->sample_period;
atomic64_set(&hwc->period_left, hwc->sample_period);
local64_set(&hwc->period_left, hwc->sample_period);
}
return 0;

5
arch/alpha/kernel/process.c
View File

@ -387,8 +387,9 @@ EXPORT_SYMBOL(dump_elf_task_fp);
* sys_execve() executes a new program.
*/
asmlinkage int
do_sys_execve(const char __user *ufilename, char __user * __user *argv,
char __user * __user *envp, struct pt_regs *regs)
do_sys_execve(const char __user *ufilename,
const char __user *const __user *argv,
const char __user *const __user *envp, struct pt_regs *regs)
{
int error;
char *filename;

3
arch/alpha/kernel/proto.h
View File

@ -156,9 +156,6 @@ extern void SMC669_Init(int);
/* es1888.c */
extern void es1888_init(void);
/* ns87312.c */
extern void ns87312_enable_ide(long ide_base);
/* ../lib/fpreg.c */
extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
extern unsigned long alpha_read_fp_reg (unsigned long reg);

19
arch/alpha/kernel/sys_cabriolet.c
View File

@ -33,7 +33,7 @@
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"
/* Note mask bit is true for DISABLED irqs. */
static unsigned long cached_irq_mask = ~0UL;
@ -235,18 +235,31 @@ cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
return COMMON_TABLE_LOOKUP;
}
static inline void __init
cabriolet_enable_ide(void)
{
if (pc873xx_probe() == -1) {
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
} else {
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
pc873xx_get_model(), pc873xx_get_base());
pc873xx_enable_ide();
}
}
static inline void __init
cabriolet_init_pci(void)
{
common_init_pci();
ns87312_enable_ide(0x398);
cabriolet_enable_ide();
}
static inline void __init
cia_cab_init_pci(void)
{
cia_init_pci();
ns87312_enable_ide(0x398);
cabriolet_enable_ide();
}
/*

11
arch/alpha/kernel/sys_takara.c
View File

@ -29,7 +29,7 @@
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"
/* Note mask bit is true for DISABLED irqs. */
static unsigned long cached_irq_mask[2] = { -1, -1 };
@ -264,7 +264,14 @@ takara_init_pci(void)
alpha_mv.pci_map_irq = takara_map_irq_srm;
cia_init_pci();
ns87312_enable_ide(0x26e);
if (pc873xx_probe() == -1) {
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
} else {
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
pc873xx_get_model(), pc873xx_get_base());
pc873xx_enable_ide();
}
}

4
arch/arm/Kconfig
View File

@ -1601,6 +1601,7 @@ config ZRELADDR
ARCH_ORION5X ||\
ARCH_SPEAR3XX ||\
ARCH_SPEAR6XX ||\
ARCH_TEGRA ||\
ARCH_U8500 ||\
ARCH_VERSATILE ||\
ARCH_W90X900
@ -1622,7 +1623,8 @@ config ZRELADDR
default 0x40008000 if ARCH_STMP378X ||\
ARCH_STMP37XX ||\
ARCH_SH7372 ||\
ARCH_SH7377
ARCH_SH7377 ||\
ARCH_S5PV310
default 0x50008000 if ARCH_S3C64XX ||\
ARCH_SH7367
default 0x60008000 if ARCH_VEXPRESS

3
arch/arm/Makefile
View File

@ -21,6 +21,9 @@ GZFLAGS :=-9
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
KBUILD_CFLAGS +=$(call cc-option,-marm,)
# Never generate .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
# Do not use arch/arm/defconfig - it's always outdated.
# Select a platform tht is kept up-to-date
KBUILD_DEFCONFIG := versatile_defconfig

3
arch/arm/configs/omap_4430sdp_defconfig
View File

@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP4=y
# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_DM_TIMER=y

17
arch/arm/include/asm/ptrace.h
View File

@ -158,15 +158,24 @@ struct pt_regs {
*/
static inline int valid_user_regs(struct pt_regs *regs)
{
if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
return 1;
unsigned long mode = regs->ARM_cpsr & MODE_MASK;
/*
* Always clear the F (FIQ) and A (delayed abort) bits
*/
regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
if (mode == USR_MODE)
return 1;
if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
return 1;
}
/*
* Force CPSR to something logical...
*/
regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
if (!(elf_hwcap & HWCAP_26BIT))
regs->ARM_cpsr |= USR_MODE;

1
arch/arm/include/asm/unistd.h
View File

@ -392,6 +392,7 @@
#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363)
#define __NR_perf_event_open (__NR_SYSCALL_BASE+364)
#define __NR_recvmmsg (__NR_SYSCALL_BASE+365)
#define __NR_accept4 (__NR_SYSCALL_BASE+366)
/*
* The following SWIs are ARM private.

1
arch/arm/kernel/calls.S
View File

@ -375,6 +375,7 @@
CALL(sys_rt_tgsigqueueinfo)
CALL(sys_perf_event_open)
/* 365 */ CALL(sys_recvmmsg)
CALL(sys_accept4)
#ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted

2
arch/arm/kernel/etm.c
View File

@ -230,7 +230,7 @@ static void etm_dump(void)
etb_lock(t);
}
static void sysrq_etm_dump(int key, struct tty_struct *tty)
static void sysrq_etm_dump(int key)
{
dev_dbg(tracer.dev, "Dumping ETB buffer\n");
etm_dump();

2
arch/arm/kernel/kgdb.c
View File

@ -79,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
return;
/* Initialize to zero */
for (regno = 0; regno < GDB_MAX_REGS; regno++)
for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
gdb_regs[regno] = 0;
/* Otherwise, we have only some registers from switch_to() */

14
arch/arm/kernel/sys_arm.c
View File

@ -62,8 +62,9 @@ asmlinkage int sys_vfork(struct pt_regs *regs)
/* sys_execve() executes a new program.
* This is called indirectly via a small wrapper
*/
asmlinkage int sys_execve(const char __user *filenamei, char __user * __user *argv,
char __user * __user *envp, struct pt_regs *regs)
asmlinkage int sys_execve(const char __user *filenamei,
const char __user *const __user *argv,
const char __user *const __user *envp, struct pt_regs *regs)
{
int error;
char * filename;
@ -78,14 +79,17 @@ out:
return error;
}
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
struct pt_regs regs;
int ret;
memset(&regs, 0, sizeof(struct pt_regs));
ret = do_execve(filename, (char __user * __user *)argv,
(char __user * __user *)envp, &regs);
ret = do_execve(filename,
(const char __user *const __user *)argv,
(const char __user *const __user *)envp, &regs);
if (ret < 0)
goto out;

4
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -279,13 +279,13 @@ static void __init eukrea_cpuimx27_init(void)
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif

4
arch/arm/mach-imx/mach-pca100.c
View File

@ -419,13 +419,13 @@ static void __init pca100_init(void)
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
#endif

2
arch/arm/mach-mx25/mach-cpuimx25.c
View File

@ -138,7 +138,7 @@ static void __init eukrea_cpuimx25_init(void)
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg, &otg_pdata);
}

2
arch/arm/mach-mx3/mach-cpuimx35.c
View File

@ -192,7 +192,7 @@ static void __init mxc_board_init(void)
#if defined(CONFIG_USB_ULPI)
if (otg_mode_host) {
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
}

1
arch/arm/mach-omap2/Makefile
View File

@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a
AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a
# Functions loaded to SRAM

14
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
struct omap_clk *c;
u32 cpu_clkflg = CK_3XXX;
if (cpu_is_omap34xx()) {
if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
} else if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_3XXX;
cpu_clkflg |= CK_343X;
@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
cpu_mask |= RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3430ES2;
}
} else if (cpu_is_omap3517()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3517;
} else if (cpu_is_omap3505()) {
cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
cpu_clkflg |= CK_3505;
}
if (omap3_has_192mhz_clk())

2
arch/arm/mach-omap2/id.c
View File

@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
default:
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
break;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_2;

6
arch/arm/mach-omap2/include/mach/entry-macro.S
View File

@ -177,7 +177,10 @@ omap_irq_base: .word 0
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
#endif
#endif /* MULTI_OMAP2 */
#ifdef CONFIG_SMP
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt
@ -205,8 +208,7 @@ omap_irq_base: .word 0
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
#endif
#endif /* MULTI_OMAP2 */
#endif /* CONFIG_SMP */
.macro irq_prio_table
.endm

3
arch/arm/mach-omap2/omap-smp.c
View File

@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb();
set_event();
dsb_sev();
mb();
}

4
arch/arm/mach-omap2/pm34xx.c
View File

@ -480,7 +480,9 @@ void omap_sram_idle(void)
}
/* Disable IO-PAD and IO-CHAIN wakeup */
if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
if (omap3_has_io_wakeup() &&
(per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)) {
prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
omap3_disable_io_chain();
}

2
arch/arm/mach-s3c2410/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s3c64xx/include/mach/vmalloc.h
View File

@ -15,6 +15,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5p6440/include/mach/vmalloc.h
View File

@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5p6442/include/mach/vmalloc.h
View File

@ -12,6 +12,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5pv210/include/mach/vmalloc.h
View File

@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xE0000000)
#define VMALLOC_END (0xE0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */

82
arch/arm/mach-s5pv310/clock.c
View File

@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000,
};
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
};
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
};
static struct clk *clkset_moutcore_list[] = {
[0] = &clk_mout_apll.clk,
[0] = &clk_sclk_apll.clk,
[1] = &clk_mout_mpll.clk,
};
@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
static struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_corebus = {
@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
static struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_mout_apll.clk,
[1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_aclk_200 = {
@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
};
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
static struct clk init_clocks_disable[] = {
{
.name = "timers",
@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
};
static struct clk init_clocks[] = {
/* Nothing here yet */
{
.name = "uart",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 4,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.id = 5,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
};
static struct clk *clkset_group_list[] = {
@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
.enable = s5pv310_clk_ip_peril_ctrl,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_sclk_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_moutcore,
@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
__raw_readl(S5P_EPLL_CON1), pll_4500);
__raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4502);
__raw_readl(S5P_VPLL_CON1), pll_4650);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;

10
arch/arm/mach-s5pv310/cpu.c
View File

@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
},
};

11
arch/arm/mach-s5pv310/include/mach/irqs.h
View File

@ -15,12 +15,14 @@
#include <plat/irqs.h>
/* Private Peripheral Interrupt */
/* PPI: Private Peripheral Interrupt */
#define IRQ_PPI(x) S5P_IRQ(x+16)
#define IRQ_LOCALTIMER IRQ_PPI(13)
/* Shared Peripheral Interrupt */
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
#define IRQ_EINT0 IRQ_SPI(40)
@ -36,7 +38,7 @@
#define IRQ_PCIE IRQ_SPI(50)
#define IRQ_SYSTEM_TIMER IRQ_SPI(51)
#define IRQ_MFC IRQ_SPI(52)
#define IRQ_WTD IRQ_SPI(53)
#define IRQ_WDT IRQ_SPI(53)
#define IRQ_AUDIO_SS IRQ_SPI(54)
#define IRQ_AC97 IRQ_SPI(55)
#define IRQ_SPDIF IRQ_SPI(56)
@ -67,8 +69,9 @@
#define IRQ_IIC COMBINER_IRQ(27, 0)
/* Set the default NR_IRQS */
#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
#define MAX_COMBINER_NR 39
#endif /* ASM_ARCH_IRQS_H */
#endif /* __ASM_ARCH_IRQS_H */

16
arch/arm/mach-s5pv310/include/mach/map.h
View File

@ -23,12 +23,16 @@
#include <plat/map-s5p.h>
#define S5PV310_PA_SYSRAM (0x02025000)
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5PV310_PA_SYSCON (0x10020000)
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5PV310_PA_CMU (0x10030000)
#define S5PV310_PA_WATCHDOG (0x10060000)
#define S5PV310_PA_COMBINER (0x10448000)
@ -39,8 +43,12 @@
#define S5PV310_PA_GIC_DIST (0x10501000)
#define S5PV310_PA_L2CC (0x10502000)
#define S5PV310_PA_GPIO (0x11000000)
#define S5P_PA_GPIO S5PV310_PA_GPIO
#define S5PV310_PA_GPIO1 (0x11400000)
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
#define S5P_PA_GPIO S5PV310_PA_GPIO1
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_UART (0x13800000)
@ -63,6 +71,10 @@
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV310_PA_UART
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
#define S3C_PA_IIC S5PV310_PA_IIC0
#define S3C_PA_WDT S5PV310_PA_WATCHDOG

59
arch/arm/mach-s5pv310/include/mach/regs-clock.h
View File

@ -15,48 +15,49 @@
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_INFORM0 S5P_CLKREG(0x800)
#define S5P_EPLL_CON0 S5P_CLKREG(0x1C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x1C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x1C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x1C124)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x20200)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
#define S5P_APLL_LOCK S5P_CLKREG(0x24000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x24004)
#define S5P_APLL_CON0 S5P_CLKREG(0x24100)
#define S5P_APLL_CON1 S5P_CLKREG(0x24104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x24108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x2410C)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x24200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x24500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

2
arch/arm/mach-s5pv310/include/mach/vmalloc.h
View File

@ -17,6 +17,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
#define VMALLOC_END (0xF0000000)
#define VMALLOC_END (0xF0000000UL)
#endif /* __ASM_ARCH_VMALLOC_H */

2
arch/arm/mach-s5pv310/platsmp.c
View File

@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
}
}

2
arch/arm/mach-tegra/board-harmony.c
View File

@ -91,10 +91,8 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
{
mi->nr_banks = 2;
mi->bank[0].start = PHYS_OFFSET;
mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = 448 * SZ_1M;
mi->bank[1].start = SZ_512M;
mi->bank[1].node = PHYS_TO_NID(SZ_512M);
mi->bank[1].size = SZ_512M;
}

2
arch/arm/mach-tegra/include/mach/vmalloc.h
View File

@ -23,6 +23,6 @@
#include <asm/sizes.h>
#define VMALLOC_END 0xFE000000
#define VMALLOC_END 0xFE000000UL
#endif

7
arch/arm/plat-omap/include/plat/smp.h
View File

@ -19,13 +19,6 @@
#include <asm/hardware/gic.h>
/*
* set_event() is used to wake up secondary core from wfe using sev. ROM
* code puts the second core into wfe(standby).
*
*/
#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);

2
arch/arm/plat-s5p/include/plat/map-s5p.h
View File

@ -17,6 +17,7 @@
#define S5P_VA_GPIO S3C_ADDR(0x00500000)
#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
#define S5P_VA_SROMC S3C_ADDR(0x01100000)
#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
@ -29,6 +30,7 @@
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
#define S5P_VA_L2CC S3C_ADDR(0x00900000)
#define S5P_VA_CMU S3C_ADDR(0x00920000)
#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_VA_UART0 S5P_VA_UART(0)

2
arch/arm/plat-samsung/dev-hsmmc.c
View File

@ -70,4 +70,6 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
set->host_caps = pd->host_caps;
}

2
arch/arm/plat-samsung/dev-hsmmc1.c
View File

@ -70,4 +70,6 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
set->host_caps = pd->host_caps;
}

2
arch/arm/plat-samsung/dev-hsmmc2.c
View File

@ -71,4 +71,6 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
set->host_caps = pd->host_caps;
}

5
arch/avr32/kernel/process.c
View File

@ -384,8 +384,9 @@ asmlinkage int sys_vfork(struct pt_regs *regs)
}
asmlinkage int sys_execve(const char __user *ufilename,
char __user *__user *uargv,
char __user *__user *uenvp, struct pt_regs *regs)
const char __user *const __user *uargv,
const char __user *const __user *uenvp,
struct pt_regs *regs)
{
int error;
char *filename;

4
arch/avr32/kernel/sys_avr32.c
View File

@ -7,7 +7,9 @@
*/
#include <linux/unistd.h>
int kernel_execve(const char *file, char **argv, char **envp)
int kernel_execve(const char *file,
const char *const *argv,
const char *const *envp)
{
register long scno asm("r8") = __NR_execve;
register long sc1 asm("r12") = (long)file;

6
arch/blackfin/include/asm/bfin_sport.h
View File

@ -115,12 +115,6 @@ struct sport_register {
#endif
/* Workaround defBF*.h SPORT MMRs till they get cleansed */
#undef DTYPE_NORM
#undef SLEN
#undef SP_WOFF
#undef SP_WSIZE
/* SPORT_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */

17
arch/blackfin/include/asm/bitops.h
View File

@ -22,7 +22,9 @@
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/const_hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/ext2-non-atomic.h>
#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/minix.h>
@ -115,7 +117,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
* of bits set) of a N-bit word
*/
static inline unsigned int hweight32(unsigned int w)
static inline unsigned int __arch_hweight32(unsigned int w)
{
unsigned int res;
@ -125,19 +127,20 @@ static inline unsigned int hweight32(unsigned int w)
return res;
}
static inline unsigned int hweight64(__u64 w)
static inline unsigned int __arch_hweight64(__u64 w)
{
return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w);
return __arch_hweight32((unsigned int)(w >> 32)) +
__arch_hweight32((unsigned int)w);
}
static inline unsigned int hweight16(unsigned int w)
static inline unsigned int __arch_hweight16(unsigned int w)
{
return hweight32(w & 0xffff);
return __arch_hweight32(w & 0xffff);
}
static inline unsigned int hweight8(unsigned int w)
static inline unsigned int __arch_hweight8(unsigned int w)
{
return hweight32(w & 0xff);
return __arch_hweight32(w & 0xff);
}
#endif /* _BLACKFIN_BITOPS_H */

5
arch/blackfin/include/asm/unistd.h
View File

@ -389,8 +389,11 @@
#define __NR_rt_tgsigqueueinfo 368
#define __NR_perf_event_open 369
#define __NR_recvmmsg 370
#define __NR_fanotify_init 371
#define __NR_fanotify_mark 372
#define __NR_prlimit64 373
#define __NR_syscall 371
#define __NR_syscall 374
#define NR_syscalls __NR_syscall
/* Old optional stuff no one actually uses */

4
arch/blackfin/kernel/process.c
View File

@ -209,7 +209,9 @@ copy_thread(unsigned long clone_flags,
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char __user *name, char __user * __user *argv, char __user * __user *envp)
asmlinkage int sys_execve(const char __user *name,
const char __user *const __user *argv,
const char __user *const __user *envp)
{
int error;
char *filename;

82
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View File

@ -913,88 +913,6 @@
#define PH6 0x0040
#define PH7 0x0080
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

1
arch/blackfin/mach-bf527/boards/cm_bf527.c
View File

@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf527/boards/ezbrd.c
View File

@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf527/boards/ezkit.c
View File

@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

82
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View File

@ -922,88 +922,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

92
arch/blackfin/mach-bf533/include/mach/defBF532.h
View File

@ -509,98 +509,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__)
# define SLEN 0x001F /*TX Word Length */
#else
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
/* SLEN defined above */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */

80
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -1241,86 +1241,6 @@
#define PH14 0x4000
#define PH15 0x8000
/* ******************* SERIAL PORT MASKS **************************************/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* Transmit Enable */
#define ITCLK 0x0002 /* Internal Transmit Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* Transmit Bit Order */
#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_TCR2 Masks and Macro */
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#define TXSE 0x0100 /* TX Secondary Enable */
#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* Receive Enable */
#define IRCLK 0x0002 /* Internal Receive Clock Select */
#define DTYPE_NORM 0x0004 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* Receive Bit Order */
#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
#define RFSR 0x0400 /* Receive Frame Sync Required Select */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define LARFS 0x2000 /* Late Receive Frame Sync Select */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
#define RUVF 0x0002 /* Sticky Receive Underflow Status */
#define ROVF 0x0004 /* Sticky Receive Overflow Status */
#define TXF 0x0008 /* Transmit FIFO Full Status */
#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
#define TXHRE 0x0040 /* Transmit Hold Register Empty */
/* SPORTx_MCMC1 Macros */
#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/* SPORTx_MCMC2 Masks */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */

107
arch/blackfin/mach-bf538/include/mach/defBF539.h
View File

@ -1610,113 +1610,6 @@
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define TULAW DTYPE_ULAW /* Compand Using u-Law */
#define TALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_TCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR1 Deprecated Masks */
#define RULAW DTYPE_ULAW /* Compand Using u-Law */
#define RALAW DTYPE_ALAW /* Compand Using A-Law */
/* SPORTx_RCR2 Masks */
#ifdef _MISRA_RULES
#define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */
#else
#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
#endif /* _MISRA_RULES */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#ifdef _MISRA_RULES
#define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#else
#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
#endif /* _MISRA_RULES */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0xF000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */
#define PORT_EN 0x0001 /* PPI Port Enable */

1
arch/blackfin/mach-bf548/boards/cm_bf548.c
View File

@ -706,7 +706,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

1
arch/blackfin/mach-bf548/boards/ezkit.c
View File

@ -849,7 +849,6 @@ static struct mtd_partition partition_info[] = {
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),

67
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View File

@ -2221,73 +2221,6 @@
#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
/* Bit masks for SPORTx_TCR1 */
#define TCKFE 0x4000 /* Clock Falling Edge Select */
#define LATFS 0x2000 /* Late Transmit Frame Sync */
#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
#define TFSR 0x400 /* Transmit Frame Sync Required Select */
#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
#define TLSBIT 0x10 /* Transmit Bit Order */
#define TDTYPE 0xc /* Data Formatting Type Select */
#define ITCLK 0x2 /* Internal Transmit Clock Select */
#define TSPEN 0x1 /* Transmit Enable */
/* Bit masks for SPORTx_TCR2 */
#define TRFST 0x400 /* Left/Right Order */
#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
#define TXSE 0x100 /* TxSEC Enable */
#define SLEN_T 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_RCR1 */
#define RCKFE 0x4000 /* Clock Falling Edge Select */
#define LARFS 0x2000 /* Late Receive Frame Sync */
#define LRFS 0x1000 /* Low Receive Frame Sync Select */
#define RFSR 0x400 /* Receive Frame Sync Required Select */
#define IRFS 0x200 /* Internal Receive Frame Sync Select */
#define RLSBIT 0x10 /* Receive Bit Order */
#define RDTYPE 0xc /* Data Formatting Type Select */
#define IRCLK 0x2 /* Internal Receive Clock Select */
#define RSPEN 0x1 /* Receive Enable */
/* Bit masks for SPORTx_RCR2 */
#define RRFST 0x400 /* Left/Right Order */
#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
#define RXSE 0x100 /* RxSEC Enable */
#define SLEN_R 0x1f /* SPORT Word Length */
/* Bit masks for SPORTx_STAT */
#define TXHRE 0x40 /* Transmit Hold Register Empty */
#define TOVF 0x20 /* Sticky Transmit Overflow Status */
#define TUVF 0x10 /* Sticky Transmit Underflow Status */
#define TXF 0x8 /* Transmit FIFO Full Status */
#define ROVF 0x4 /* Sticky Receive Overflow Status */
#define RUVF 0x2 /* Sticky Receive Underflow Status */
#define RXNE 0x1 /* Receive FIFO Not Empty Status */
/* Bit masks for SPORTx_MCMC1 */
#define SP_WSIZE 0xf000 /* Window Size */
#define SP_WOFF 0x3ff /* Windows Offset */
/* Bit masks for SPORTx_MCMC2 */
#define MFD 0xf000 /* Multi channel Frame Delay */
#define FSDR 0x80 /* Frame Sync to Data Relationship */
#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
#define MCCRM 0x3 /* 2X Clock Recovery Mode */
/* Bit masks for SPORTx_CHNL */
#define CUR_CHNL 0x3ff /* Current Channel Indicator */
/* Bit masks for UARTx_LCR */
#if 0

60
arch/blackfin/mach-bf561/include/mach/defBF561.h
View File

@ -1007,66 +1007,6 @@
#define IREN_P 0x01
#define UCEN_P 0x00
/* ********** SERIAL PORT MASKS ********************** */
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F /*TX Word Length */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F /*RX Word Length */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
/*SPORTx_STAT Masks */
#define RXNE 0x0001 /*RX FIFO Not Empty Status */
#define RUVF 0x0002 /*RX Underflow Status */
#define ROVF 0x0004 /*RX Overflow Status */
#define TXF 0x0008 /*TX FIFO Full Status */
#define TUVF 0x0010 /*TX Underflow Status */
#define TOVF 0x0020 /*TX Overflow Status */
#define TXHRE 0x0040 /*TX Hold Register Empty */
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
/* PPI_CONTROL Masks */

3
arch/blackfin/mach-common/entry.S
View File

@ -1628,6 +1628,9 @@ ENTRY(_sys_call_table)
.long _sys_rt_tgsigqueueinfo
.long _sys_perf_event_open
.long _sys_recvmmsg /* 370 */
.long _sys_fanotify_init
.long _sys_fanotify_mark
.long _sys_prlimit64
.rept NR_syscalls-(.-_sys_call_table)/4
.long _sys_ni_syscall

4
arch/cris/arch-v10/kernel/process.c
View File

@ -204,7 +204,9 @@ asmlinkage int sys_vfork(long r10, long r11, long r12, long r13, long mof, long
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char *fname, char **argv, char **envp,
asmlinkage int sys_execve(const char *fname,
const char *const *argv,
const char *const *envp,
long r13, long mof, long srp,
struct pt_regs *regs)
{

6
arch/cris/arch-v32/kernel/process.c
View File

@ -218,8 +218,10 @@ sys_vfork(long r10, long r11, long r12, long r13, long mof, long srp,
/* sys_execve() executes a new program. */
asmlinkage int
sys_execve(const char *fname, char **argv, char **envp, long r13, long mof, long srp,
struct pt_regs *regs)
sys_execve(const char *fname,
const char *const *argv,
const char *const *envp, long r13, long mof, long srp,
struct pt_regs *regs)
{
int error;
char *filename;

5
arch/frv/kernel/process.c
View File

@ -250,8 +250,9 @@ int copy_thread(unsigned long clone_flags,
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char __user *name, char __user * __user *argv,
char __user * __user *envp)
asmlinkage int sys_execve(const char __user *name,
const char __user *const __user *argv,
const char __user *const __user *envp)
{
int error;
char * filename;

15
arch/h8300/include/asm/atomic.h
View File

@ -18,7 +18,8 @@
static __inline__ int atomic_add_return(int i, atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
ret = v->counter += i;
local_irq_restore(flags);
@ -30,7 +31,8 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
static __inline__ int atomic_sub_return(int i, atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
ret = v->counter -= i;
local_irq_restore(flags);
@ -42,7 +44,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v)
static __inline__ int atomic_inc_return(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
v->counter++;
ret = v->counter;
@ -64,7 +67,8 @@ static __inline__ int atomic_inc_return(atomic_t *v)
static __inline__ int atomic_dec_return(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
--v->counter;
ret = v->counter;
@ -76,7 +80,8 @@ static __inline__ int atomic_dec_return(atomic_t *v)
static __inline__ int atomic_dec_and_test(atomic_t *v)
{
int ret,flags;
unsigned long flags;
int ret;
local_irq_save(flags);
--v->counter;
ret = v->counter;

4
arch/h8300/include/asm/system.h
View File

@ -3,6 +3,8 @@
#include <linux/linkage.h>
struct pt_regs;
/*
* switch_to(n) should switch tasks to task ptr, first checking that
* ptr isn't the current task, in which case it does nothing. This
@ -155,6 +157,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
#define arch_align_stack(x) (x)
void die(char *str, struct pt_regs *fp, unsigned long err);
extern void die(const char *str, struct pt_regs *fp, unsigned long err);
#endif /* _H8300_SYSTEM_H */

5
arch/h8300/kernel/process.c
View File

@ -212,7 +212,10 @@ int copy_thread(unsigned long clone_flags,
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char *name, char **argv, char **envp,int dummy,...)
asmlinkage int sys_execve(const char *name,
const char *const *argv,
const char *const *envp,
int dummy, ...)
{
int error;
char * filename;

8
arch/h8300/kernel/sys_h8300.c
View File

@ -51,11 +51,13 @@ asmlinkage void syscall_print(void *dummy,...)
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register long res __asm__("er0");
register char *const *_c __asm__("er3") = envp;
register char *const *_b __asm__("er2") = argv;
register const char *const *_c __asm__("er3") = envp;
register const char *const *_b __asm__("er2") = argv;
register const char * _a __asm__("er1") = filename;
__asm__ __volatile__ ("mov.l %1,er0\n\t"
"trapa #0\n\t"

2
arch/h8300/kernel/traps.c
View File

@ -96,7 +96,7 @@ static void dump(struct pt_regs *fp)
printk("\n\n");
}
void die(char *str, struct pt_regs *fp, unsigned long err)
void die(const char *str, struct pt_regs *fp, unsigned long err)
{
static int diecount;

2
arch/ia64/hp/sim/simserial.c
View File

@ -149,7 +149,7 @@ static void receive_chars(struct tty_struct *tty)
ch = ia64_ssc(0, 0, 0, 0,
SSC_GETCHAR);
while (!ch);
handle_sysrq(ch, NULL);
handle_sysrq(ch);
}
#endif
seen_esc = 0;

2
arch/ia64/include/asm/unistd.h
View File

@ -356,8 +356,6 @@ asmlinkage unsigned long sys_mmap2(
int fd, long pgoff);
struct pt_regs;
struct sigaction;
long sys_execve(const char __user *filename, char __user * __user *argv,
char __user * __user *envp, struct pt_regs *regs);
asmlinkage long sys_ia64_pipe(void);
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,

4
arch/ia64/kernel/process.c
View File

@ -633,7 +633,9 @@ dump_fpu (struct pt_regs *pt, elf_fpregset_t dst)
}
long
sys_execve (const char __user *filename, char __user * __user *argv, char __user * __user *envp,
sys_execve (const char __user *filename,
const char __user *const __user *argv,
const char __user *const __user *envp,
struct pt_regs *regs)
{
char *fname;

4
arch/m32r/kernel/process.c
View File

@ -289,8 +289,8 @@ asmlinkage int sys_vfork(unsigned long r0, unsigned long r1, unsigned long r2,
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char __user *ufilename,
char __user * __user *uargv,
char __user * __user *uenvp,
const char __user *const __user *uargv,
const char __user *const __user *uenvp,
unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, struct pt_regs regs)
{

4
arch/m32r/kernel/sys_m32r.c
View File

@ -93,7 +93,9 @@ asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register long __scno __asm__ ("r7") = __NR_execve;
register long __arg3 __asm__ ("r2") = (long)(envp);

13
arch/m68k/include/asm/ide.h
View File

@ -1,6 +1,4 @@
/*
* linux/include/asm-m68k/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
@ -34,6 +32,8 @@
#include <asm/io.h>
#include <asm/irq.h>
#ifdef CONFIG_MMU
/*
* Get rid of defs from io.h - ide has its private and conflicting versions
* Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we
@ -53,5 +53,14 @@
#define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
#define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
#else
#define __ide_mm_insw(port, addr, n) io_insw((unsigned int)port, addr, n)
#define __ide_mm_insl(port, addr, n) io_insl((unsigned int)port, addr, n)
#define __ide_mm_outsw(port, addr, n) io_outsw((unsigned int)port, addr, n)
#define __ide_mm_outsl(port, addr, n) io_outsl((unsigned int)port, addr, n)
#endif /* CONFIG_MMU */
#endif /* __KERNEL__ */
#endif /* _M68K_IDE_H */

4
arch/m68k/kernel/process.c
View File

@ -315,7 +315,9 @@ EXPORT_SYMBOL(dump_fpu);
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char __user *name, char __user * __user *argv, char __user * __user *envp)
asmlinkage int sys_execve(const char __user *name,
const char __user *const __user *argv,
const char __user *const __user *envp)
{
int error;
char * filename;

4
arch/m68k/kernel/sys_m68k.c
View File

@ -459,7 +459,9 @@ asmlinkage int sys_getpagesize(void)
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register long __res asm ("%d0") = __NR_execve;
register long __a asm ("%d1") = (long)(filename);

14
arch/m68knommu/kernel/process.c
View File

@ -316,14 +316,14 @@ void dump(struct pt_regs *fp)
fp->d0, fp->d1, fp->d2, fp->d3);
printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
fp->d4, fp->d5, fp->a0, fp->a1);
printk(KERN_EMERG "\nUSP: %08x TRAPFRAME: %08x\n",
(unsigned int) rdusp(), (unsigned int) fp);
printk(KERN_EMERG "\nUSP: %08x TRAPFRAME: %p\n",
(unsigned int) rdusp(), fp);
printk(KERN_EMERG "\nCODE:");
tp = ((unsigned char *) fp->pc) - 0x20;
for (sp = (unsigned long *) tp, i = 0; (i < 0x40); i += 4) {
if ((i % 0x10) == 0)
printk(KERN_EMERG "%08x: ", (int) (tp + i));
printk(KERN_EMERG "%p: ", tp + i);
printk("%08x ", (int) *sp++);
}
printk(KERN_EMERG "\n");
@ -332,7 +332,7 @@ void dump(struct pt_regs *fp)
tp = ((unsigned char *) fp) - 0x40;
for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) {
if ((i % 0x10) == 0)
printk(KERN_EMERG "%08x: ", (int) (tp + i));
printk(KERN_EMERG "%p: ", tp + i);
printk("%08x ", (int) *sp++);
}
printk(KERN_EMERG "\n");
@ -341,7 +341,7 @@ void dump(struct pt_regs *fp)
tp = (unsigned char *) (rdusp() - 0x10);
for (sp = (unsigned long *) tp, i = 0; (i < 0x80); i += 4) {
if ((i % 0x10) == 0)
printk(KERN_EMERG "%08x: ", (int) (tp + i));
printk(KERN_EMERG "%p: ", tp + i);
printk("%08x ", (int) *sp++);
}
printk(KERN_EMERG "\n");
@ -350,7 +350,9 @@ void dump(struct pt_regs *fp)
/*
* sys_execve() executes a new program.
*/
asmlinkage int sys_execve(const char *name, char **argv, char **envp)
asmlinkage int sys_execve(const char *name,
const char *const *argv,
const char *const *envp)
{
int error;
char * filename;

4
arch/m68knommu/kernel/sys_m68k.c
View File

@ -44,7 +44,9 @@ asmlinkage int sys_getpagesize(void)
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register long __res asm ("%d0") = __NR_execve;
register long __a asm ("%d1") = (long)(filename);

2
arch/m68knommu/kernel/vmlinux.lds.S
View File

@ -150,6 +150,8 @@ SECTIONS {
_sdata = . ;
DATA_DATA
CACHELINE_ALIGNED_DATA(32)
PAGE_ALIGNED_DATA(PAGE_SIZE)
*(.data..shared_aligned)
INIT_TASK_DATA(THREAD_SIZE)
_edata = . ;
} > DATA

2
arch/microblaze/kernel/prom_parse.c
View File

@ -73,7 +73,7 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
/* We can only get here if we hit a P2P bridge with no node,
* let's do standard swizzling and try again
*/
lspec = of_irq_pci_swizzle(PCI_SLOT(pdev->devfn), lspec);
lspec = pci_swizzle_interrupt_pin(pdev, lspec);
pdev = ppdev;
}

10
arch/microblaze/kernel/sys_microblaze.c
View File

@ -47,8 +47,10 @@ asmlinkage long microblaze_clone(int flags, unsigned long stack, struct pt_regs
return do_fork(flags, stack, regs, 0, NULL, NULL);
}
asmlinkage long microblaze_execve(const char __user *filenamei, char __user *__user *argv,
char __user *__user *envp, struct pt_regs *regs)
asmlinkage long microblaze_execve(const char __user *filenamei,
const char __user *const __user *argv,
const char __user *const __user *envp,
struct pt_regs *regs)
{
int error;
char *filename;
@ -77,7 +79,9 @@ asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register const char *__a __asm__("r5") = filename;
register const void *__b __asm__("r6") = argv;

5
arch/microblaze/pci/pci-common.c
View File

@ -27,10 +27,11 @@
#include <linux/irq.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
@ -1077,7 +1078,7 @@ void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
struct dev_archdata *sd = &dev->dev.archdata;
/* Setup OF node pointer in archdata */
sd->of_node = pci_device_to_OF_node(dev);
dev->dev.of_node = pci_device_to_OF_node(dev);
/* Fixup NUMA node as it may not be setup yet by the generic
* code and is needed by the DMA init

1
arch/microblaze/pci/xilinx_pci.c
View File

@ -16,6 +16,7 @@
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <asm/io.h>

10
arch/mips/kernel/syscall.c
View File

@ -258,8 +258,10 @@ asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs)
error = PTR_ERR(filename);
if (IS_ERR(filename))
goto out;
error = do_execve(filename, (char __user *__user *) (long)regs.regs[5],
(char __user *__user *) (long)regs.regs[6], &regs);
error = do_execve(filename,
(const char __user *const __user *) (long)regs.regs[5],
(const char __user *const __user *) (long)regs.regs[6],
&regs);
putname(filename);
out:
@ -436,7 +438,9 @@ asmlinkage void bad_stack(void)
* Do a system call from kernel instead of calling sys_execve so we
* end up with proper pt_regs.
*/
int kernel_execve(const char *filename, char *const argv[], char *const envp[])
int kernel_execve(const char *filename,
const char *const argv[],
const char *const envp[])
{
register unsigned long __a0 asm("$4") = (unsigned long) filename;
register unsigned long __a1 asm("$5") = (unsigned long) argv;

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