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viafb: reset correct PLL 

Looks like we did reset the PLL of the (whatever) engine instead of
the PLL of the secondary display (IGA2, LCDCK). This patch fixes it.

Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Joseph Chan <JosephChan@via.com.tw>
This commit is contained in:
Florian Tobias Schandinat 2010-07-28 00:57:18 +00:00
parent b4aaa78f4c
commit e3812ce4ee
1 changed files with 2 additions and 2 deletions
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4
drivers/video/via/hw.c
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@ -1688,8 +1688,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
}
if (set_iga == IGA2) {
viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
}
/* Fire! */