USB: r8a66597-hcd: fixes some problem
This patch incorporates some updates. Updates include: - Fix the problem that control transfer might fail - Change from GFP_KERNEL to GFP_ATOMIC - Clean up some coding style issue Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Yoshihiro Shimoda
Greg Kroah-Hartman
parent
809a58b896
commit
e294531dc9
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@ -35,10 +35,8 @@
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#include <linux/interrupt.h>
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#include <linux/usb.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include "../core/hcd.h"
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#include "r8a66597.h"
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@ -54,16 +52,21 @@ static const char hcd_name[] = "r8a66597_hcd";
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/* module parameters */
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static unsigned short clock = XTAL12;
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module_param(clock, ushort, 0644);
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MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=0)");
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MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
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"(default=0)");
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static unsigned short vif = LDRV;
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module_param(vif, ushort, 0644);
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MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)");
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static unsigned short endian = 0;
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static unsigned short endian;
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module_param(endian, ushort, 0644);
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MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)");
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MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
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static unsigned short irq_sense = INTL;
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module_param(irq_sense, ushort, 0644);
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MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0(default=32)");
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MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0 "
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"(default=32)");
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static void packet_write(struct r8a66597 *r8a66597, u16 pipenum);
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static int r8a66597_get_frame(struct usb_hcd *hcd);
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@ -308,7 +311,7 @@ static int make_r8a66597_device(struct r8a66597 *r8a66597,
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struct r8a66597_device *dev;
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int usb_address = urb->setup_packet[2]; /* urb->pipe is address 0 */
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dev = kzalloc(sizeof(struct r8a66597_device), GFP_KERNEL);
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dev = kzalloc(sizeof(struct r8a66597_device), GFP_ATOMIC);
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if (dev == NULL)
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return -ENOMEM;
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@ -611,33 +614,33 @@ static u16 get_empty_pipenum(struct r8a66597 *r8a66597,
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u16 array[R8A66597_MAX_NUM_PIPE], i = 0, min;
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memset(array, 0, sizeof(array));
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switch(ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
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case USB_ENDPOINT_XFER_BULK:
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switch (ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
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case USB_ENDPOINT_XFER_BULK:
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if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
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array[i++] = 4;
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else {
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array[i++] = 3;
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array[i++] = 5;
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}
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break;
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case USB_ENDPOINT_XFER_INT:
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break;
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case USB_ENDPOINT_XFER_INT:
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if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) {
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array[i++] = 6;
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array[i++] = 7;
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array[i++] = 8;
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} else
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array[i++] = 9;
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break;
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case USB_ENDPOINT_XFER_ISOC:
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break;
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case USB_ENDPOINT_XFER_ISOC:
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if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
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array[i++] = 2;
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else
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array[i++] = 1;
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break;
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default:
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err("Illegal type");
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return 0;
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}
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break;
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default:
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err("Illegal type");
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return 0;
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}
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i = 1;
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min = array[0];
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@ -654,7 +657,7 @@ static u16 get_r8a66597_type(__u8 type)
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{
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u16 r8a66597_type;
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switch(type) {
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switch (type) {
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case USB_ENDPOINT_XFER_BULK:
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r8a66597_type = R8A66597_BULK;
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break;
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@ -874,7 +877,7 @@ static void r8a66597_usb_preconnect(struct r8a66597 *r8a66597, int port)
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{
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r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_CONNECTION)
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| (1 << USB_PORT_FEAT_C_CONNECTION);
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r8a66597_write(r8a66597, (u16)~DTCH, get_intsts_reg(port));
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r8a66597_write(r8a66597, ~DTCH, get_intsts_reg(port));
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r8a66597_bset(r8a66597, DTCHE, get_intenb_reg(port));
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}
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@ -917,7 +920,7 @@ static void prepare_setup_packet(struct r8a66597 *r8a66597,
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r8a66597_write(r8a66597, make_devsel(td->address) | td->maxpacket,
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DCPMAXP);
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r8a66597_write(r8a66597, (u16)~(SIGN | SACK), INTSTS1);
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r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
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for (i = 0; i < 4; i++) {
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r8a66597_write(r8a66597, p[i], setup_addr);
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@ -948,19 +951,18 @@ static void prepare_packet_read(struct r8a66597 *r8a66597,
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pipe_irq_disable(r8a66597, td->pipenum);
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pipe_setting(r8a66597, td);
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pipe_stop(r8a66597, td->pipe);
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r8a66597_write(r8a66597, (u16)~(1 << td->pipenum),
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BRDYSTS);
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r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS);
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if (td->pipe->pipetre) {
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r8a66597_write(r8a66597, TRCLR,
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td->pipe->pipetre);
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td->pipe->pipetre);
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r8a66597_write(r8a66597,
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(urb->transfer_buffer_length
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+ td->maxpacket - 1)
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/ td->maxpacket,
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td->pipe->pipetrn);
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(urb->transfer_buffer_length
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+ td->maxpacket - 1)
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/ td->maxpacket,
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td->pipe->pipetrn);
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r8a66597_bset(r8a66597, TRENB,
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td->pipe->pipetre);
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td->pipe->pipetre);
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}
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pipe_start(r8a66597, td->pipe);
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@ -991,7 +993,7 @@ static void prepare_packet_write(struct r8a66597 *r8a66597,
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if (td->pipe->pipetre)
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r8a66597_bclr(r8a66597, TRENB, td->pipe->pipetre);
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}
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r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), BRDYSTS);
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r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS);
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fifo_change_from_pipe(r8a66597, td->pipe);
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tmp = r8a66597_read(r8a66597, td->pipe->fifoctr);
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@ -1009,21 +1011,21 @@ static void prepare_status_packet(struct r8a66597 *r8a66597,
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struct urb *urb = td->urb;
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r8a66597_pipe_toggle(r8a66597, td->pipe, 1);
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pipe_stop(r8a66597, td->pipe);
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if (urb->setup_packet[0] & USB_ENDPOINT_DIR_MASK) {
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r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG);
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r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
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r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
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r8a66597_write(r8a66597, BVAL | BCLR, CFIFOCTR);
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r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS);
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r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
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r8a66597_write(r8a66597, BCLR, CFIFOCTR);
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r8a66597_write(r8a66597, BVAL, CFIFOCTR);
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enable_irq_empty(r8a66597, 0);
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} else {
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r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
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r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
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r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
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r8a66597_write(r8a66597, BCLR, CFIFOCTR);
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r8a66597_write(r8a66597, (u16)~BRDY0, BRDYSTS);
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r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS);
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enable_irq_ready(r8a66597, 0);
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}
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enable_irq_nrdy(r8a66597, 0);
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@ -1269,7 +1271,7 @@ static void packet_write(struct r8a66597 *r8a66597, u16 pipenum)
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/* write fifo */
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if (pipenum > 0)
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r8a66597_write(r8a66597, (u16)~(1 << pipenum), BEMPSTS);
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r8a66597_write(r8a66597, ~(1 << pipenum), BEMPSTS);
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if (urb->transfer_buffer) {
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r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size);
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if (!usb_pipebulk(urb->pipe) || td->maxpacket != size)
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@ -1362,7 +1364,7 @@ static void irq_pipe_ready(struct r8a66597 *r8a66597)
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mask = r8a66597_read(r8a66597, BRDYSTS)
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& r8a66597_read(r8a66597, BRDYENB);
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r8a66597_write(r8a66597, (u16)~mask, BRDYSTS);
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r8a66597_write(r8a66597, ~mask, BRDYSTS);
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if (mask & BRDY0) {
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td = r8a66597_get_td(r8a66597, 0);
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if (td && td->type == USB_PID_IN)
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@ -1397,7 +1399,7 @@ static void irq_pipe_empty(struct r8a66597 *r8a66597)
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mask = r8a66597_read(r8a66597, BEMPSTS)
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& r8a66597_read(r8a66597, BEMPENB);
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r8a66597_write(r8a66597, (u16)~mask, BEMPSTS);
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r8a66597_write(r8a66597, ~mask, BEMPSTS);
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if (mask & BEMP0) {
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cfifo_change(r8a66597, 0);
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td = r8a66597_get_td(r8a66597, 0);
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@ -1434,7 +1436,7 @@ static void irq_pipe_nrdy(struct r8a66597 *r8a66597)
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mask = r8a66597_read(r8a66597, NRDYSTS)
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& r8a66597_read(r8a66597, NRDYENB);
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r8a66597_write(r8a66597, (u16)~mask, NRDYSTS);
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r8a66597_write(r8a66597, ~mask, NRDYSTS);
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if (mask & NRDY0) {
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cfifo_change(r8a66597, 0);
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set_urb_error(r8a66597, 0);
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@ -1488,14 +1490,14 @@ static irqreturn_t r8a66597_irq(struct usb_hcd *hcd)
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mask0 = intsts0 & intenb0 & (BEMP | NRDY | BRDY);
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if (mask2) {
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if (mask2 & ATTCH) {
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r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS2);
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r8a66597_write(r8a66597, ~ATTCH, INTSTS2);
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r8a66597_bclr(r8a66597, ATTCHE, INTENB2);
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/* start usb bus sampling */
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start_root_hub_sampling(r8a66597, 1);
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}
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if (mask2 & DTCH) {
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r8a66597_write(r8a66597, (u16)~DTCH, INTSTS2);
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r8a66597_write(r8a66597, ~DTCH, INTSTS2);
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r8a66597_bclr(r8a66597, DTCHE, INTENB2);
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r8a66597_usb_disconnect(r8a66597, 1);
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}
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@ -1503,24 +1505,24 @@ static irqreturn_t r8a66597_irq(struct usb_hcd *hcd)
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if (mask1) {
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if (mask1 & ATTCH) {
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r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS1);
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r8a66597_write(r8a66597, ~ATTCH, INTSTS1);
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r8a66597_bclr(r8a66597, ATTCHE, INTENB1);
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/* start usb bus sampling */
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start_root_hub_sampling(r8a66597, 0);
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}
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if (mask1 & DTCH) {
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r8a66597_write(r8a66597, (u16)~DTCH, INTSTS1);
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r8a66597_write(r8a66597, ~DTCH, INTSTS1);
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r8a66597_bclr(r8a66597, DTCHE, INTENB1);
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r8a66597_usb_disconnect(r8a66597, 0);
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}
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if (mask1 & SIGN) {
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r8a66597_write(r8a66597, (u16)~SIGN, INTSTS1);
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r8a66597_write(r8a66597, ~SIGN, INTSTS1);
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set_urb_error(r8a66597, 0);
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check_next_phase(r8a66597);
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}
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if (mask1 & SACK) {
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r8a66597_write(r8a66597, (u16)~SACK, INTSTS1);
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r8a66597_write(r8a66597, ~SACK, INTSTS1);
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check_next_phase(r8a66597);
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}
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}
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@ -1663,13 +1665,9 @@ static int check_pipe_config(struct r8a66597 *r8a66597, struct urb *urb)
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static int r8a66597_start(struct usb_hcd *hcd)
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{
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struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd);
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int ret;
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hcd->state = HC_STATE_RUNNING;
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if ((ret = enable_controller(r8a66597)) < 0)
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return ret;
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return 0;
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return enable_controller(r8a66597);
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}
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static void r8a66597_stop(struct usb_hcd *hcd)
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@ -1696,13 +1694,12 @@ static void set_address_zero(struct r8a66597 *r8a66597, struct urb *urb)
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static struct r8a66597_td *r8a66597_make_td(struct r8a66597 *r8a66597,
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struct urb *urb,
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struct usb_host_endpoint *hep,
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gfp_t mem_flags)
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struct usb_host_endpoint *hep)
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{
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struct r8a66597_td *td;
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u16 pipenum;
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td = kzalloc(sizeof(struct r8a66597_td), mem_flags);
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td = kzalloc(sizeof(struct r8a66597_td), GFP_ATOMIC);
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if (td == NULL)
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return NULL;
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@ -1741,7 +1738,8 @@ static int r8a66597_urb_enqueue(struct usb_hcd *hcd,
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}
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if (!hep->hcpriv) {
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hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), mem_flags);
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hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe),
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GFP_ATOMIC);
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if (!hep->hcpriv) {
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ret = -ENOMEM;
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goto error;
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@ -1755,7 +1753,7 @@ static int r8a66597_urb_enqueue(struct usb_hcd *hcd,
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init_pipe_config(r8a66597, urb);
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set_address_zero(r8a66597, urb);
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td = r8a66597_make_td(r8a66597, urb, hep, mem_flags);
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td = r8a66597_make_td(r8a66597, urb, hep);
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if (td == NULL) {
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ret = -ENOMEM;
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goto error;
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@ -203,14 +203,14 @@
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#define DTLN 0x0FFF /* b11-0: FIFO received data length */
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/* Interrupt Enable Register 0 */
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#define VBSE 0x8000 /* b15: VBUS interrupt */
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#define RSME 0x4000 /* b14: Resume interrupt */
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#define SOFE 0x2000 /* b13: Frame update interrupt */
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#define DVSE 0x1000 /* b12: Device state transition interrupt */
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#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
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#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
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#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
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#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
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#define VBSE 0x8000 /* b15: VBUS interrupt */
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#define RSME 0x4000 /* b14: Resume interrupt */
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#define SOFE 0x2000 /* b13: Frame update interrupt */
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#define DVSE 0x1000 /* b12: Device state transition interrupt */
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#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
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#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
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#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
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#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
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/* Interrupt Enable Register 1 */
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#define OVRCRE 0x8000 /* b15: Over-current interrupt */
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@ -268,16 +268,16 @@
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#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
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/* Interrupt Status Register 0 */
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#define VBINT 0x8000 /* b15: VBUS interrupt */
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#define RESM 0x4000 /* b14: Resume interrupt */
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#define SOFR 0x2000 /* b13: SOF frame update interrupt */
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#define DVST 0x1000 /* b12: Device state transition interrupt */
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#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
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#define BEMP 0x0400 /* b10: Buffer empty interrupt */
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#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
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#define BRDY 0x0100 /* b8: Buffer ready interrupt */
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#define VBSTS 0x0080 /* b7: VBUS input port */
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#define DVSQ 0x0070 /* b6-4: Device state */
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#define VBINT 0x8000 /* b15: VBUS interrupt */
|
||||
#define RESM 0x4000 /* b14: Resume interrupt */
|
||||
#define SOFR 0x2000 /* b13: SOF frame update interrupt */
|
||||
#define DVST 0x1000 /* b12: Device state transition interrupt */
|
||||
#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
|
||||
#define BEMP 0x0400 /* b10: Buffer empty interrupt */
|
||||
#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
|
||||
#define BRDY 0x0100 /* b8: Buffer ready interrupt */
|
||||
#define VBSTS 0x0080 /* b7: VBUS input port */
|
||||
#define DVSQ 0x0070 /* b6-4: Device state */
|
||||
#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
|
||||
#define DS_SPD_ADDR 0x0060 /* Suspend Address */
|
||||
#define DS_SPD_DFLT 0x0050 /* Suspend Default */
|
||||
|
|
@ -315,13 +315,10 @@
|
|||
/* Micro Frame Number Register */
|
||||
#define UFRNM 0x0007 /* b2-0: Micro frame number */
|
||||
|
||||
/* USB Address / Low Power Status Recovery Register */
|
||||
//#define USBADDR 0x007F /* b6-0: USB address */
|
||||
|
||||
/* Default Control Pipe Maxpacket Size Register */
|
||||
/* Pipe Maxpacket Size Register */
|
||||
#define DEVSEL 0xF000 /* b15-14: Device address select */
|
||||
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
|
||||
#define DEVSEL 0xF000 /* b15-14: Device address select */
|
||||
#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
|
||||
|
||||
/* Default Control Pipe Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
|
|
@ -366,21 +363,21 @@
|
|||
#define MXPS 0x07FF /* b10-0: Maxpacket size */
|
||||
|
||||
/* Pipe Cycle Configuration Register */
|
||||
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
|
||||
#define IITV 0x0007 /* b2-0: Isochronous interval */
|
||||
#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
|
||||
#define IITV 0x0007 /* b2-0: Isochronous interval */
|
||||
|
||||
/* Pipex Control Register */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define ATREPM 0x0400 /* b10: Auto repeat mode */
|
||||
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
#define BSTS 0x8000 /* b15: Buffer status */
|
||||
#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
|
||||
#define CSCLR 0x2000 /* b13: complete-split status clear */
|
||||
#define CSSTS 0x1000 /* b12: complete-split status */
|
||||
#define ATREPM 0x0400 /* b10: Auto repeat mode */
|
||||
#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
|
||||
#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
|
||||
#define SQSET 0x0080 /* b7: Sequence toggle bit set */
|
||||
#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
|
||||
#define PBUSY 0x0020 /* b5: pipe busy */
|
||||
#define PID 0x0003 /* b1-0: Response PID */
|
||||
|
||||
/* PIPExTRE */
|
||||
#define TRENB 0x0200 /* b9: Transaction counter enable */
|
||||
|
|
@ -407,15 +404,15 @@
|
|||
#define make_devsel(addr) (addr << 12)
|
||||
|
||||
struct r8a66597_pipe_info {
|
||||
u16 pipenum;
|
||||
u16 address; /* R8A66597 HCD usb addres */
|
||||
u16 epnum;
|
||||
u16 maxpacket;
|
||||
u16 type;
|
||||
u16 bufnum;
|
||||
u16 buf_bsize;
|
||||
u16 interval;
|
||||
u16 dir_in;
|
||||
u16 pipenum;
|
||||
u16 address; /* R8A66597 HCD usb addres */
|
||||
u16 epnum;
|
||||
u16 maxpacket;
|
||||
u16 type;
|
||||
u16 bufnum;
|
||||
u16 buf_bsize;
|
||||
u16 interval;
|
||||
u16 dir_in;
|
||||
};
|
||||
|
||||
struct r8a66597_pipe {
|
||||
|
|
|
|||
Reference in New Issue