ARM: entry: data abort: use r2 as base of pt_regs rather than stack
Now that we pass r2 into these helper functions as the pointer to pt_regs, use r2 as the base of the registers on the stack rather than using the stack pointer directly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
da74047257
commit
e22c12f914
2 changed files with 19 additions and 19 deletions
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@ -73,11 +73,11 @@ ENTRY(v4t_late_abort)
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrhpre:
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@ -88,14 +88,14 @@ ENTRY(v4t_late_abort)
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tst r8, #1 << 22 @ if (immediate offset)
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andne r6, r8, #0xf00 @ { immediate high nibble
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orrne r6, r5, r6, lsr #4 @ combine nibbles } else
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ldreq r6, [sp, r5, lsl #2] @ { load Rm value }
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ldreq r6, [r2, r5, lsl #2] @ { load Rm value }
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrpreconst:
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@ -105,11 +105,11 @@ ENTRY(v4t_late_abort)
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movs r9, r8, lsl #20 @ Get offset
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beq do_DataAbort @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r9, lsr #20 @ Undo increment
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addeq r7, r7, r9, lsr #20 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrprereg:
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@ -117,7 +117,7 @@ ENTRY(v4t_late_abort)
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beq do_DataAbort @ no writeback -> no fixup
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
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ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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and r7, r8, #0x70 @ get shift type
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@ -201,11 +201,11 @@ ENTRY(v4t_late_abort)
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movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
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adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
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and r6, r6, #15 @ number of regs to transfer
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ldr r7, [sp, #13 << 2]
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ldr r7, [r2, #13 << 2]
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tst r8, #1 << 11
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addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
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subne r7, r7, r6, lsl #2 @ decrement SP if POP
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str r7, [sp, #13 << 2]
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str r7, [r2, #13 << 2]
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b do_DataAbort
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.data_thumb_ldmstm:
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@ -217,8 +217,8 @@ ENTRY(v4t_late_abort)
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add r6, r6, r9, lsr #2
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add r6, r6, r6, lsr #4
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and r5, r8, #7 << 8
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ldr r7, [sp, r5, lsr #6]
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ldr r7, [r2, r5, lsr #6]
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and r6, r6, #15 @ number of regs to transfer
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sub r7, r7, r6, lsl #2 @ always decrement
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str r7, [sp, r5, lsr #6]
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str r7, [r2, r5, lsr #6]
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b do_DataAbort
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@ -96,20 +96,20 @@ ENTRY(cpu_arm6_data_abort)
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrpreconst:
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@ -119,11 +119,11 @@ ENTRY(cpu_arm6_data_abort)
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movs r9, r8, lsl #20 @ Get offset
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beq do_DataAbort @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r9, lsr #20 @ Undo increment
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addeq r7, r7, r9, lsr #20 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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str r7, [r2, r5, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrprereg:
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@ -131,7 +131,7 @@ ENTRY(cpu_arm6_data_abort)
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beq do_DataAbort @ no writeback -> no fixup
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
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ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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and r7, r8, #0x70 @ get shift type
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