OMAPDSS: DISPC: Add naive threshold calc for fifomerge
Take fifo merge into use by implementing a rather naive fifo merge threshold calculation: keep the low threshold always the same, but increase the high threshold when fifo merge is used. This should greatly increase the time between pixel data fetches from SDRAM, as the usable fifo size is much larger. However, it probably won't help for fifo underflows, as the low threshols is kept the same. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -1072,13 +1072,33 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
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*/
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unsigned buf_unit = dss_feat_get_buffer_size_unit();
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unsigned fifo_size, burst_size;
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unsigned ovl_fifo_size, total_fifo_size, burst_size;
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int i;
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burst_size = dispc_ovl_get_burst_size(plane);
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fifo_size = dispc_ovl_get_fifo_size(plane);
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ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
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*fifo_low = fifo_size - burst_size;
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*fifo_high = fifo_size - buf_unit;
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if (use_fifomerge) {
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total_fifo_size = 0;
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for (i = 0; i < omap_dss_get_num_overlays(); ++i)
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total_fifo_size += dispc_ovl_get_fifo_size(i);
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} else {
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total_fifo_size = ovl_fifo_size;
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}
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/*
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* We use the same low threshold for both fifomerge and non-fifomerge
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* cases, but for fifomerge we calculate the high threshold using the
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* combined fifo size
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*/
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if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
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*fifo_low = ovl_fifo_size - burst_size * 2;
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*fifo_high = total_fifo_size - burst_size;
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} else {
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*fifo_low = ovl_fifo_size - burst_size;
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*fifo_high = total_fifo_size - buf_unit;
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}
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}
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static void dispc_ovl_set_fir(enum omap_plane plane,
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@ -370,7 +370,8 @@ static const struct omap_dss_features omap3430_dss_features = {
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FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
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FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
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FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
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FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE,
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FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
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FEAT_OMAP3_DSI_FIFO_BUG,
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.num_mgrs = 2,
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.num_ovls = 3,
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@ -394,7 +395,8 @@ static const struct omap_dss_features omap3630_dss_features = {
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FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
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FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
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FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
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FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE,
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FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
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FEAT_OMAP3_DSI_FIFO_BUG,
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.num_mgrs = 2,
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.num_ovls = 3,
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@ -59,6 +59,8 @@ enum dss_feat_id {
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FEAT_ALPHA_FIXED_ZORDER = 1 << 26,
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FEAT_ALPHA_FREE_ZORDER = 1 << 27,
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FEAT_FIFO_MERGE = 1 << 28,
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/* An unknown HW bug causing the normal FIFO thresholds not to work */
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FEAT_OMAP3_DSI_FIFO_BUG = 1 << 29,
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};
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/* DSS register field id */
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