[ARM] 5530/1: Freescale STMP: get rid of HW_zzz macros [1/3]
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
dmitry pervushin
Russell King
parent
b4380b8e58
commit
e0421bbe64
7 changed files with 421 additions and 894 deletions
|
|
@ -1,11 +1,9 @@
|
|||
/*
|
||||
* STMP APBH Register Definitions
|
||||
* stmp378x: APBH register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -20,69 +18,84 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_APBH
|
||||
#define _MACH_REGS_APBH
|
||||
|
||||
#ifndef __ARCH_ARM___APBH_H
|
||||
#define __ARCH_ARM___APBH_H 1
|
||||
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
|
||||
#define REGS_APBH_PHYS 0x80004000
|
||||
#define REGS_APBH_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_APBH_CTRL0 0x0
|
||||
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
|
||||
#define BP_APBH_CTRL0_RESET_CHANNEL 16
|
||||
#define BM_APBH_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBH_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define REGS_APBH_BASE (REGS_BASE + 0x4000)
|
||||
#define REGS_APBH_BASE_PHYS (0x80004000)
|
||||
#define REGS_APBH_SIZE 0x00002000
|
||||
HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00000000)
|
||||
#define HW_APBH_CTRL0_ADDR (REGS_APBH_BASE + 0x00000000)
|
||||
#define BM_APBH_CTRL0_SFTRST 0x80000000
|
||||
#define BM_APBH_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000
|
||||
#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000
|
||||
#define BP_APBH_CTRL0_RESET_CHANNEL 16
|
||||
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
|
||||
#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
|
||||
(((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL)
|
||||
HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x00000010)
|
||||
#define HW_APBH_CTRL1_ADDR (REGS_APBH_BASE + 0x00000010)
|
||||
HW_REGISTER(HW_APBH_CTRL2, REGS_APBH_BASE, 0x00000020)
|
||||
HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x00000030)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x00000040, 0x70)
|
||||
#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0
|
||||
#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF
|
||||
#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x00000050, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x00000060, 0x70)
|
||||
#define BP_APBH_CHn_CMD_XFER_COUNT 16
|
||||
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
|
||||
(((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT)
|
||||
#define BP_APBH_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BF_APBH_CHn_CMD_CMDWORDS(v) \
|
||||
(((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS)
|
||||
#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100
|
||||
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
|
||||
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
|
||||
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
|
||||
#define BP_APBH_CHn_CMD_COMMAND 0
|
||||
#define BM_APBH_CHn_CMD_COMMAND 0x00000003
|
||||
#define BF_APBH_CHn_CMD_COMMAND(v) \
|
||||
(((v) << 0) & BM_APBH_CHn_CMD_COMMAND)
|
||||
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x00000070, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x00000080, 0x70)
|
||||
#define BP_APBH_CHn_SEMA_PHORE 16
|
||||
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BF_APBH_CHn_SEMA_PHORE(v) \
|
||||
(((v) << 16) & BM_APBH_CHn_SEMA_PHORE)
|
||||
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
|
||||
(((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x00000090, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0x000000a0, 0x70)
|
||||
HW_REGISTER_0(HW_APBH_VERSION, REGS_APBH_BASE, 0x000003f0)
|
||||
#endif /* __ARCH_ARM___APBH_H */
|
||||
#define HW_APBH_CTRL1 0x10
|
||||
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
|
||||
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
|
||||
|
||||
#define HW_APBH_CTRL2 0x20
|
||||
|
||||
#define HW_APBH_DEVSEL 0x30
|
||||
|
||||
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_NXTCMDAR 0x50
|
||||
|
||||
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
|
||||
#define BM_APBH_CHn_CMD_COMMAND 0x00000003
|
||||
#define BP_APBH_CHn_CMD_COMMAND 0
|
||||
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
|
||||
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
|
||||
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBH_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBH_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_SEMA 0x80
|
||||
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBH_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,10 +1,9 @@
|
|||
/*
|
||||
* STMP APBX Register Definitions
|
||||
* stmp378x: APBX register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
|
|
@ -19,61 +18,102 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ARCH_ARM___APBX_H
|
||||
#define __ARCH_ARM___APBX_H 1
|
||||
#ifndef _MACH_REGS_APBX
|
||||
#define _MACH_REGS_APBX
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
|
||||
#define REGS_APBX_PHYS 0x80024000
|
||||
#define REGS_APBX_SIZE 0x2000
|
||||
|
||||
#define HW_APBX_CTRL0 0x0
|
||||
#define BM_APBX_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBX_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_APBX_CTRL1 0x10
|
||||
|
||||
#define HW_APBX_CTRL2 0x20
|
||||
|
||||
#define HW_APBX_CHANNEL_CTRL 0x30
|
||||
#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
|
||||
#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
|
||||
|
||||
#define HW_APBX_DEVSEL 0x40
|
||||
|
||||
#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_NXTCMDAR 0x110
|
||||
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
|
||||
#define BP_APBX_CHn_CMD_COMMAND 0
|
||||
#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
|
||||
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
|
||||
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBX_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBX_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_BAR 0x130
|
||||
|
||||
#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_SEMA 0x140
|
||||
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBX_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
||||
#define REGS_APBX_BASE (REGS_BASE + 0x24000)
|
||||
#define REGS_APBX_BASE_PHYS (0x80024000)
|
||||
#define REGS_APBX_SIZE 0x00002000
|
||||
HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00000000)
|
||||
#define HW_APBX_CTRL0_ADDR (REGS_APBX_BASE + 0x00000000)
|
||||
#define BM_APBX_CTRL0_SFTRST 0x80000000
|
||||
#define BM_APBX_CTRL0_CLKGATE 0x40000000
|
||||
HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x00000010)
|
||||
HW_REGISTER(HW_APBX_CTRL2, REGS_APBX_BASE, 0x00000020)
|
||||
HW_REGISTER(HW_APBX_CHANNEL_CTRL, REGS_APBX_BASE, 0x00000030)
|
||||
#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
|
||||
#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
|
||||
#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \
|
||||
(((v) << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL) & \
|
||||
BM_APBX_CHANNEL_CTRL_RESET_CHANNEL)
|
||||
HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x00000040)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x00000100, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x00000110, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x00000120, 0x70)
|
||||
#define BP_APBX_CHn_CMD_XFER_COUNT 16
|
||||
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BF_APBX_CHn_CMD_XFER_COUNT(v) \
|
||||
(((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT)
|
||||
#define BP_APBX_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BF_APBX_CHn_CMD_CMDWORDS(v) \
|
||||
(((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS)
|
||||
#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
|
||||
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
|
||||
#define BP_APBX_CHn_CMD_COMMAND 0
|
||||
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
|
||||
#define BF_APBX_CHn_CMD_COMMAND(v) \
|
||||
(((v) << 0) & BM_APBX_CHn_CMD_COMMAND)
|
||||
#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x00000130, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x00000140, 0x70)
|
||||
#define BP_APBX_CHn_SEMA_PHORE 16
|
||||
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BF_APBX_CHn_SEMA_PHORE(v) \
|
||||
(((v) << 16) & BM_APBX_CHn_SEMA_PHORE)
|
||||
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
|
||||
(((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x00000150, 0x70)
|
||||
HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0x00000160, 0x70)
|
||||
HW_REGISTER_0(HW_APBX_VERSION, REGS_APBX_BASE, 0x00000800)
|
||||
#endif /* __ARCH_ARM___APBX_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* STMP CLKCTRL Register Definitions
|
||||
* stmp378x: CLKCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
|
|
@ -18,259 +18,71 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_CLKCTRL
|
||||
#define _MACH_REGS_CLKCTRL
|
||||
|
||||
#ifndef __ARCH_ARM___CLKCTRL_H
|
||||
#define __ARCH_ARM___CLKCTRL_H 1
|
||||
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
|
||||
#define REGS_CLKCTRL_PHYS 0x80040000
|
||||
#define REGS_CLKCTRL_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_CLKCTRL_PLLCTRL0 0x0
|
||||
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
|
||||
|
||||
#define REGS_CLKCTRL_BASE (REGS_BASE + 0x40000)
|
||||
#define REGS_CLKCTRL_BASE_PHYS (0x80040000)
|
||||
#define REGS_CLKCTRL_SIZE 0x00002000
|
||||
HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00000000)
|
||||
#define HW_CLKCTRL_PLLCTRL0_ADDR (REGS_CLKCTRL_BASE + 0x00000000)
|
||||
#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
|
||||
#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
|
||||
#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
|
||||
#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
|
||||
#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
|
||||
#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
|
||||
#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
|
||||
(((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
|
||||
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
|
||||
#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
|
||||
HW_REGISTER_0(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x00000010)
|
||||
#define HW_CLKCTRL_PLLCTRL1_ADDR (REGS_CLKCTRL_BASE + 0x00000010)
|
||||
#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
|
||||
#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
|
||||
#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
|
||||
#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
|
||||
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
|
||||
HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x00000020)
|
||||
#define HW_CLKCTRL_CPU_ADDR (REGS_CLKCTRL_BASE + 0x00000020)
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
|
||||
#define BP_CLKCTRL_CPU_DIV_XTAL 16
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
|
||||
#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
|
||||
#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BF_CLKCTRL_CPU_DIV_CPU(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
|
||||
HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x00000030)
|
||||
#define HW_CLKCTRL_HBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000030)
|
||||
#define BM_CLKCTRL_HBUS_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
|
||||
#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
|
||||
#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
|
||||
#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
|
||||
#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
|
||||
#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
|
||||
#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
|
||||
#define BP_CLKCTRL_HBUS_SLOW_DIV 16
|
||||
#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
|
||||
#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
|
||||
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BF_CLKCTRL_HBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x00000040)
|
||||
#define HW_CLKCTRL_XBUS_ADDR (REGS_CLKCTRL_BASE + 0x00000040)
|
||||
#define BM_CLKCTRL_XBUS_BUSY 0x80000000
|
||||
#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_XBUS_DIV 0
|
||||
#define BM_CLKCTRL_XBUS_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_XBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XBUS_DIV)
|
||||
HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x00000050)
|
||||
#define HW_CLKCTRL_XTAL_ADDR (REGS_CLKCTRL_BASE + 0x00000050)
|
||||
#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
|
||||
#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
|
||||
#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
|
||||
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
|
||||
#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
|
||||
#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
|
||||
#define BP_CLKCTRL_XTAL_DIV_UART 0
|
||||
#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
|
||||
#define BF_CLKCTRL_XTAL_DIV_UART(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
|
||||
HW_REGISTER_0(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x00000060)
|
||||
#define HW_CLKCTRL_PIX_ADDR (REGS_CLKCTRL_BASE + 0x00000060)
|
||||
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_PIX_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
|
||||
#define BP_CLKCTRL_PIX_DIV 0
|
||||
#define BM_CLKCTRL_PIX_DIV 0x00000FFF
|
||||
#define BF_CLKCTRL_PIX_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PIX_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x00000070)
|
||||
#define HW_CLKCTRL_SSP_ADDR (REGS_CLKCTRL_BASE + 0x00000070)
|
||||
#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP_DIV 0
|
||||
#define BM_CLKCTRL_SSP_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x00000080)
|
||||
#define HW_CLKCTRL_GPMI_ADDR (REGS_CLKCTRL_BASE + 0x00000080)
|
||||
#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_GPMI_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_GPMI_DIV 0
|
||||
#define BM_CLKCTRL_GPMI_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_GPMI_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_GPMI_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x00000090)
|
||||
#define HW_CLKCTRL_SPDIF_ADDR (REGS_CLKCTRL_BASE + 0x00000090)
|
||||
#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
|
||||
HW_REGISTER_0(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0x000000a0)
|
||||
#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + 0x000000a0)
|
||||
#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
|
||||
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
|
||||
#define BP_CLKCTRL_EMI_DIV_XTAL 8
|
||||
#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
|
||||
#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
|
||||
#define BP_CLKCTRL_EMI_DIV_EMI 0
|
||||
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
|
||||
#define BF_CLKCTRL_EMI_DIV_EMI(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
|
||||
HW_REGISTER_0(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0x000000b0)
|
||||
#define HW_CLKCTRL_IR_ADDR (REGS_CLKCTRL_BASE + 0x000000b0)
|
||||
#define BM_CLKCTRL_IR_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
|
||||
#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
|
||||
#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
|
||||
#define BP_CLKCTRL_IR_IROV_DIV 16
|
||||
#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
|
||||
#define BF_CLKCTRL_IR_IROV_DIV(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
|
||||
#define BP_CLKCTRL_IR_IR_DIV 0
|
||||
#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_IR_IR_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0x000000c0)
|
||||
#define HW_CLKCTRL_SAIF_ADDR (REGS_CLKCTRL_BASE + 0x000000c0)
|
||||
#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SAIF_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
|
||||
#define BP_CLKCTRL_SAIF_DIV 0
|
||||
#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
|
||||
#define BF_CLKCTRL_SAIF_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SAIF_DIV)
|
||||
HW_REGISTER_0(HW_CLKCTRL_TV, REGS_CLKCTRL_BASE, 0x000000d0)
|
||||
#define HW_CLKCTRL_TV_ADDR (REGS_CLKCTRL_BASE + 0x000000d0)
|
||||
#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
|
||||
#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
|
||||
HW_REGISTER_0(HW_CLKCTRL_ETM, REGS_CLKCTRL_BASE, 0x000000e0)
|
||||
#define HW_CLKCTRL_ETM_ADDR (REGS_CLKCTRL_BASE + 0x000000e0)
|
||||
#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_ETM_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
|
||||
#define BP_CLKCTRL_ETM_DIV 0
|
||||
#define BM_CLKCTRL_ETM_DIV 0x0000003F
|
||||
#define BF_CLKCTRL_ETM_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_ETM_DIV)
|
||||
HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0x000000f0)
|
||||
#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + 0x000000f0)
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
|
||||
#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
|
||||
#define BP_CLKCTRL_FRAC_IOFRAC 24
|
||||
#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
|
||||
#define BF_CLKCTRL_FRAC_IOFRAC(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
|
||||
#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
|
||||
#define BP_CLKCTRL_FRAC_PIXFRAC 16
|
||||
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
|
||||
#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
|
||||
#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
|
||||
#define BP_CLKCTRL_FRAC_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
|
||||
#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
|
||||
#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
|
||||
#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
|
||||
#define BP_CLKCTRL_FRAC_CPUFRAC 0
|
||||
#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
|
||||
#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
|
||||
HW_REGISTER(HW_CLKCTRL_FRAC1, REGS_CLKCTRL_BASE, 0x00000100)
|
||||
#define HW_CLKCTRL_FRAC1_ADDR (REGS_CLKCTRL_BASE + 0x00000100)
|
||||
#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
|
||||
#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
|
||||
HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0x00000110)
|
||||
#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + 0x00000110)
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
|
||||
HW_REGISTER_0(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0x00000120)
|
||||
#define HW_CLKCTRL_RESET_ADDR (REGS_CLKCTRL_BASE + 0x00000120)
|
||||
#define BM_CLKCTRL_RESET_CHIP 0x00000002
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
HW_REGISTER_0(HW_CLKCTRL_STATUS, REGS_CLKCTRL_BASE, 0x00000130)
|
||||
#define HW_CLKCTRL_STATUS_ADDR (REGS_CLKCTRL_BASE + 0x00000130)
|
||||
#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
|
||||
#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
|
||||
#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
|
||||
(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
|
||||
HW_REGISTER_0(HW_CLKCTRL_VERSION, REGS_CLKCTRL_BASE, 0x00000140)
|
||||
#define HW_CLKCTRL_VERSION_ADDR (REGS_CLKCTRL_BASE + 0x00000140)
|
||||
#define BP_CLKCTRL_VERSION_MAJOR 24
|
||||
#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
|
||||
#define BF_CLKCTRL_VERSION_MAJOR(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
|
||||
#define BP_CLKCTRL_VERSION_MINOR 16
|
||||
#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
|
||||
#define BF_CLKCTRL_VERSION_MINOR(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
|
||||
#define BP_CLKCTRL_VERSION_STEP 0
|
||||
#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
|
||||
#define BF_CLKCTRL_VERSION_STEP(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_VERSION_STEP)
|
||||
#endif /* __ARCH_ARM___CLKCTRL_H */
|
||||
#define HW_CLKCTRL_CPU 0x20
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
|
||||
#define HW_CLKCTRL_HBUS 0x30
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
|
||||
|
||||
#define HW_CLKCTRL_XBUS 0x40
|
||||
|
||||
#define HW_CLKCTRL_XTAL 0x50
|
||||
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
|
||||
|
||||
#define HW_CLKCTRL_PIX 0x60
|
||||
#define BM_CLKCTRL_PIX_DIV 0x00000FFF
|
||||
#define BP_CLKCTRL_PIX_DIV 0
|
||||
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
|
||||
|
||||
#define HW_CLKCTRL_SSP 0x70
|
||||
|
||||
#define HW_CLKCTRL_GPMI 0x80
|
||||
|
||||
#define HW_CLKCTRL_SPDIF 0x90
|
||||
|
||||
#define HW_CLKCTRL_EMI 0xA0
|
||||
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
|
||||
#define BP_CLKCTRL_EMI_DIV_EMI 0
|
||||
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
|
||||
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
|
||||
|
||||
#define HW_CLKCTRL_IR 0xB0
|
||||
|
||||
#define HW_CLKCTRL_SAIF 0xC0
|
||||
|
||||
#define HW_CLKCTRL_TV 0xD0
|
||||
|
||||
#define HW_CLKCTRL_ETM 0xE0
|
||||
|
||||
#define HW_CLKCTRL_FRAC 0xF0
|
||||
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
|
||||
#define BP_CLKCTRL_FRAC_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
|
||||
#define BP_CLKCTRL_FRAC_PIXFRAC 16
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
|
||||
|
||||
#define HW_CLKCTRL_FRAC1 0x100
|
||||
|
||||
#define HW_CLKCTRL_CLKSEQ 0x110
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
|
||||
|
||||
#define HW_CLKCTRL_RESET 0x120
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
#define BP_CLKCTRL_RESET_DIG 0
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* STMP ICOLL Register Definitions
|
||||
* stmp378x: ICOLL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
|
|
@ -18,196 +18,28 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_ICOLL
|
||||
#define _MACH_REGS_ICOLL
|
||||
|
||||
#ifndef __ARCH_ARM___ICOLL_H
|
||||
#define __ARCH_ARM___ICOLL_H 1
|
||||
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
|
||||
#define REGS_ICOLL_PHYS 0x80000000
|
||||
#define REGS_ICOLL_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_ICOLL_VECTOR 0x0
|
||||
|
||||
#define REGS_ICOLL_BASE (REGS_BASE + 0x0)
|
||||
#define REGS_ICOLL_BASE_PHYS (0x80000000)
|
||||
#define REGS_ICOLL_SIZE 0x00002000
|
||||
HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00000000)
|
||||
#define HW_ICOLL_VECTOR_ADDR (REGS_ICOLL_BASE + 0x00000000)
|
||||
#define BP_ICOLL_VECTOR_IRQVECTOR 2
|
||||
#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC
|
||||
#define BF_ICOLL_VECTOR_IRQVECTOR(v) \
|
||||
(((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR)
|
||||
HW_REGISTER_0(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x00000010)
|
||||
#define HW_ICOLL_LEVELACK_ADDR (REGS_ICOLL_BASE + 0x00000010)
|
||||
#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
|
||||
#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
|
||||
#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \
|
||||
(((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK)
|
||||
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
|
||||
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2
|
||||
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4
|
||||
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8
|
||||
HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x00000020)
|
||||
#define HW_ICOLL_CTRL_ADDR (REGS_ICOLL_BASE + 0x00000020)
|
||||
#define BM_ICOLL_CTRL_SFTRST 0x80000000
|
||||
#define BV_ICOLL_CTRL_SFTRST__RUN 0x0
|
||||
#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1
|
||||
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
|
||||
#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0
|
||||
#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1
|
||||
#define BP_ICOLL_CTRL_VECTOR_PITCH 21
|
||||
#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000
|
||||
#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \
|
||||
(((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH)
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6
|
||||
#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7
|
||||
#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000
|
||||
#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0
|
||||
#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1
|
||||
#define BM_ICOLL_CTRL_NO_NESTING 0x00080000
|
||||
#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0
|
||||
#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1
|
||||
#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000
|
||||
#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000
|
||||
#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
|
||||
#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1
|
||||
#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000
|
||||
#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
|
||||
#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1
|
||||
HW_REGISTER(HW_ICOLL_VBASE, REGS_ICOLL_BASE, 0x00000040)
|
||||
#define HW_ICOLL_VBASE_ADDR (REGS_ICOLL_BASE + 0x00000040)
|
||||
#define BP_ICOLL_VBASE_TABLE_ADDRESS 2
|
||||
#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC
|
||||
#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \
|
||||
(((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS)
|
||||
HW_REGISTER_0(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x00000070)
|
||||
#define HW_ICOLL_STAT_ADDR (REGS_ICOLL_BASE + 0x00000070)
|
||||
#define BP_ICOLL_STAT_VECTOR_NUMBER 0
|
||||
#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F
|
||||
#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \
|
||||
(((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER)
|
||||
/*
|
||||
* multi-register-define name HW_ICOLL_RAWn
|
||||
* base 0x000000A0
|
||||
* count 4
|
||||
* offset 0x10
|
||||
*/
|
||||
HW_REGISTER_0_INDEXED(HW_ICOLL_RAWn, REGS_ICOLL_BASE, 0x000000a0, 0x10)
|
||||
#define BP_ICOLL_RAWn_RAW_IRQS 0
|
||||
#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF
|
||||
#define BF_ICOLL_RAWn_RAW_IRQS(v) (v)
|
||||
/*
|
||||
* multi-register-define name HW_ICOLL_INTERRUPTn
|
||||
* base 0x00000120
|
||||
* count 128
|
||||
* offset 0x10
|
||||
*/
|
||||
HW_REGISTER_INDEXED(HW_ICOLL_INTERRUPTn, REGS_ICOLL_BASE, 0x00000120, 0x10)
|
||||
#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010
|
||||
#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0
|
||||
#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1
|
||||
#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008
|
||||
#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0
|
||||
#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1
|
||||
#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
|
||||
#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0
|
||||
#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1
|
||||
#define BP_ICOLL_INTERRUPTn_PRIORITY 0
|
||||
#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003
|
||||
#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \
|
||||
(((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY)
|
||||
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0
|
||||
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1
|
||||
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2
|
||||
#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3
|
||||
HW_REGISTER(HW_ICOLL_DEBUG, REGS_ICOLL_BASE, 0x00001120)
|
||||
#define HW_ICOLL_DEBUG_ADDR (REGS_ICOLL_BASE + 0x00001120)
|
||||
#define BP_ICOLL_DEBUG_INSERVICE 28
|
||||
#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000
|
||||
#define BF_ICOLL_DEBUG_INSERVICE(v) \
|
||||
(((v) << 28) & BM_ICOLL_DEBUG_INSERVICE)
|
||||
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1
|
||||
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2
|
||||
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4
|
||||
#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8
|
||||
#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24
|
||||
#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000
|
||||
#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \
|
||||
(((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS)
|
||||
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1
|
||||
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2
|
||||
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4
|
||||
#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8
|
||||
#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20
|
||||
#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000
|
||||
#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \
|
||||
(((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL)
|
||||
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1
|
||||
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2
|
||||
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4
|
||||
#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8
|
||||
#define BM_ICOLL_DEBUG_FIQ 0x00020000
|
||||
#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0
|
||||
#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1
|
||||
#define BM_ICOLL_DEBUG_IRQ 0x00010000
|
||||
#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0
|
||||
#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1
|
||||
#define BP_ICOLL_DEBUG_VECTOR_FSM 0
|
||||
#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF
|
||||
#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \
|
||||
(((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM)
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100
|
||||
#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200
|
||||
HW_REGISTER(HW_ICOLL_DBGREAD0, REGS_ICOLL_BASE, 0x00001130)
|
||||
#define HW_ICOLL_DBGREAD0_ADDR (REGS_ICOLL_BASE + 0x00001130)
|
||||
#define BP_ICOLL_DBGREAD0_VALUE 0
|
||||
#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF
|
||||
#define BF_ICOLL_DBGREAD0_VALUE(v) (v)
|
||||
HW_REGISTER(HW_ICOLL_DBGREAD1, REGS_ICOLL_BASE, 0x00001140)
|
||||
#define HW_ICOLL_DBGREAD1_ADDR (REGS_ICOLL_BASE + 0x00001140)
|
||||
#define BP_ICOLL_DBGREAD1_VALUE 0
|
||||
#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF
|
||||
#define BF_ICOLL_DBGREAD1_VALUE(v) (v)
|
||||
HW_REGISTER(HW_ICOLL_DBGFLAG, REGS_ICOLL_BASE, 0x00001150)
|
||||
#define HW_ICOLL_DBGFLAG_ADDR (REGS_ICOLL_BASE + 0x00001150)
|
||||
#define BP_ICOLL_DBGFLAG_FLAG 0
|
||||
#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF
|
||||
#define BF_ICOLL_DBGFLAG_FLAG(v) \
|
||||
(((v) << 0) & BM_ICOLL_DBGFLAG_FLAG)
|
||||
/*
|
||||
* multi-register-define name HW_ICOLL_DBGREQUESTn
|
||||
* base 0x00001160
|
||||
* count 4
|
||||
* offset 0x10
|
||||
*/
|
||||
HW_REGISTER_0_INDEXED(HW_ICOLL_DBGREQUESTn, REGS_ICOLL_BASE, 0x00001160,
|
||||
0x10)
|
||||
#define BP_ICOLL_DBGREQUESTn_BITS 0
|
||||
#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF
|
||||
#define BF_ICOLL_DBGREQUESTn_BITS(v) (v)
|
||||
HW_REGISTER_0(HW_ICOLL_VERSION, REGS_ICOLL_BASE, 0x000011e0)
|
||||
#define HW_ICOLL_VERSION_ADDR (REGS_ICOLL_BASE + 0x000011e0)
|
||||
#define BP_ICOLL_VERSION_MAJOR 24
|
||||
#define BM_ICOLL_VERSION_MAJOR 0xFF000000
|
||||
#define BF_ICOLL_VERSION_MAJOR(v) \
|
||||
(((v) << 24) & BM_ICOLL_VERSION_MAJOR)
|
||||
#define BP_ICOLL_VERSION_MINOR 16
|
||||
#define BM_ICOLL_VERSION_MINOR 0x00FF0000
|
||||
#define BF_ICOLL_VERSION_MINOR(v) \
|
||||
(((v) << 16) & BM_ICOLL_VERSION_MINOR)
|
||||
#define BP_ICOLL_VERSION_STEP 0
|
||||
#define BM_ICOLL_VERSION_STEP 0x0000FFFF
|
||||
#define BF_ICOLL_VERSION_STEP(v) \
|
||||
(((v) << 0) & BM_ICOLL_VERSION_STEP)
|
||||
#endif /* __ARCH_ARM___ICOLL_H */
|
||||
#define HW_ICOLL_LEVELACK 0x10
|
||||
#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
|
||||
#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
|
||||
|
||||
#define HW_ICOLL_CTRL 0x20
|
||||
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
|
||||
#define BM_ICOLL_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_ICOLL_STAT 0x70
|
||||
|
||||
#define HW_ICOLL_INTERRUPTn 0x120
|
||||
|
||||
#define HW_ICOLL_INTERRUPTn 0x120
|
||||
#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* STMP PINCTRL Register Definitions
|
||||
* stmp378x: PINCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
|
|
@ -18,126 +18,73 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_PINCTRL
|
||||
#define _MACH_REGS_PINCTRL
|
||||
|
||||
#ifndef __ARCH_ARM___PINCTRL_H
|
||||
#define __ARCH_ARM___PINCTRL_H 1
|
||||
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
|
||||
#define REGS_PINCTRL_PHYS 0x80018000
|
||||
#define REGS_PINCTRL_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_PINCTRL_MUXSEL0 0x100
|
||||
#define HW_PINCTRL_MUXSEL1 0x110
|
||||
#define HW_PINCTRL_MUXSEL2 0x120
|
||||
#define HW_PINCTRL_MUXSEL3 0x130
|
||||
#define HW_PINCTRL_MUXSEL4 0x140
|
||||
#define HW_PINCTRL_MUXSEL5 0x150
|
||||
#define HW_PINCTRL_MUXSEL6 0x160
|
||||
#define HW_PINCTRL_MUXSEL7 0x170
|
||||
|
||||
#define REGS_PINCTRL_BASE (REGS_BASE + 0x18000)
|
||||
#define REGS_PINCTRL_BASE_PHYS (0x80018000)
|
||||
#define REGS_PINCTRL_SIZE 0x00002000
|
||||
HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0x00000000)
|
||||
#define HW_PINCTRL_CTRL_ADDR (REGS_PINCTRL_BASE + 0x00000000)
|
||||
#define BM_PINCTRL_CTRL_SFTRST 0x80000000
|
||||
#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
|
||||
#define BM_PINCTRL_CTRL_PRESENT3 0x08000000
|
||||
#define BM_PINCTRL_CTRL_PRESENT2 0x04000000
|
||||
#define BM_PINCTRL_CTRL_PRESENT1 0x02000000
|
||||
#define BM_PINCTRL_CTRL_PRESENT0 0x01000000
|
||||
#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004
|
||||
#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002
|
||||
#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x00000100)
|
||||
#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x00000100)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x00000110)
|
||||
#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x00000110)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x00000120)
|
||||
#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x00000120)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x00000130)
|
||||
#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x00000130)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x00000140)
|
||||
#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x00000140)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x00000150)
|
||||
#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x00000150)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x00000160)
|
||||
#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x00000160)
|
||||
HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x00000170)
|
||||
#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x00000170)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x00000200)
|
||||
#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x00000200)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x00000210)
|
||||
#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x00000210)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x00000220)
|
||||
#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x00000220)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x00000230)
|
||||
#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x00000230)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x00000240)
|
||||
#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x00000240)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x00000250)
|
||||
#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x00000250)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x00000260)
|
||||
#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x00000260)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x00000270)
|
||||
#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x00000270)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x00000280)
|
||||
#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x00000280)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x00000290)
|
||||
#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x00000290)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x000002a0)
|
||||
#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x000002a0)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x000002b0)
|
||||
#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x000002b0)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x000002c0)
|
||||
#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x000002c0)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x000002d0)
|
||||
#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x000002d0)
|
||||
HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x000002e0)
|
||||
#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x000002e0)
|
||||
HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x00000400)
|
||||
#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x00000400)
|
||||
HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x00000410)
|
||||
#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x00000410)
|
||||
HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x00000420)
|
||||
#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x00000420)
|
||||
HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x00000430)
|
||||
#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x00000430)
|
||||
HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x00000500)
|
||||
#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x00000500)
|
||||
HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x00000510)
|
||||
#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x00000510)
|
||||
HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x00000520)
|
||||
#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x00000520)
|
||||
HW_REGISTER(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x00000600)
|
||||
#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x00000600)
|
||||
HW_REGISTER(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x00000610)
|
||||
#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x00000610)
|
||||
HW_REGISTER(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x00000620)
|
||||
#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x00000620)
|
||||
HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x00000700)
|
||||
#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x00000700)
|
||||
HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x00000710)
|
||||
#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x00000710)
|
||||
HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x00000720)
|
||||
#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x00000720)
|
||||
HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x00000800)
|
||||
#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x00000800)
|
||||
HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x00000810)
|
||||
#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x00000810)
|
||||
HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x00000820)
|
||||
#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x00000820)
|
||||
HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x00000900)
|
||||
#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x00000900)
|
||||
HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x00000910)
|
||||
#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x00000910)
|
||||
HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x00000920)
|
||||
#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x00000920)
|
||||
HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x00000a00)
|
||||
#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x00000a00)
|
||||
HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x00000a10)
|
||||
#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x00000a10)
|
||||
HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x00000a20)
|
||||
#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x00000a20)
|
||||
HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0x00000b00)
|
||||
#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0x00000b00)
|
||||
HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0x00000b10)
|
||||
#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0x00000b10)
|
||||
HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0x00000b20)
|
||||
#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0x00000b20)
|
||||
HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0x00000c00)
|
||||
#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0x00000c00)
|
||||
HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0x00000c10)
|
||||
#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0x00000c10)
|
||||
HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0x00000c20)
|
||||
#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0x00000c20)
|
||||
#endif /* __ARCH_ARM___PINCTRL_H */
|
||||
#define HW_PINCTRL_DRIVE0 0x200
|
||||
#define HW_PINCTRL_DRIVE1 0x210
|
||||
#define HW_PINCTRL_DRIVE2 0x220
|
||||
#define HW_PINCTRL_DRIVE3 0x230
|
||||
#define HW_PINCTRL_DRIVE4 0x240
|
||||
#define HW_PINCTRL_DRIVE5 0x250
|
||||
#define HW_PINCTRL_DRIVE6 0x260
|
||||
#define HW_PINCTRL_DRIVE7 0x270
|
||||
#define HW_PINCTRL_DRIVE8 0x280
|
||||
#define HW_PINCTRL_DRIVE9 0x290
|
||||
#define HW_PINCTRL_DRIVE10 0x2A0
|
||||
#define HW_PINCTRL_DRIVE11 0x2B0
|
||||
#define HW_PINCTRL_DRIVE12 0x2C0
|
||||
#define HW_PINCTRL_DRIVE13 0x2D0
|
||||
#define HW_PINCTRL_DRIVE14 0x2E0
|
||||
|
||||
#define HW_PINCTRL_PULL0 0x400
|
||||
#define HW_PINCTRL_PULL1 0x410
|
||||
#define HW_PINCTRL_PULL2 0x420
|
||||
#define HW_PINCTRL_PULL3 0x430
|
||||
|
||||
#define HW_PINCTRL_DOUT0 0x500
|
||||
#define HW_PINCTRL_DOUT1 0x510
|
||||
#define HW_PINCTRL_DOUT2 0x520
|
||||
|
||||
#define HW_PINCTRL_DIN0 0x600
|
||||
#define HW_PINCTRL_DIN1 0x610
|
||||
#define HW_PINCTRL_DIN2 0x620
|
||||
|
||||
#define HW_PINCTRL_DOE0 0x700
|
||||
#define HW_PINCTRL_DOE1 0x710
|
||||
#define HW_PINCTRL_DOE2 0x720
|
||||
|
||||
#define HW_PINCTRL_PIN2IRQ0 0x800
|
||||
#define HW_PINCTRL_PIN2IRQ1 0x810
|
||||
#define HW_PINCTRL_PIN2IRQ2 0x820
|
||||
|
||||
#define HW_PINCTRL_IRQEN0 0x900
|
||||
#define HW_PINCTRL_IRQEN1 0x910
|
||||
#define HW_PINCTRL_IRQEN2 0x920
|
||||
|
||||
#define HW_PINCTRL_IRQLEVEL0 0xA00
|
||||
#define HW_PINCTRL_IRQLEVEL1 0xA10
|
||||
#define HW_PINCTRL_IRQLEVEL2 0xA20
|
||||
|
||||
#define HW_PINCTRL_IRQPOL0 0xB00
|
||||
#define HW_PINCTRL_IRQPOL1 0xB10
|
||||
#define HW_PINCTRL_IRQPOL2 0xB20
|
||||
|
||||
#define HW_PINCTRL_IRQSTAT0 0xC00
|
||||
#define HW_PINCTRL_IRQSTAT1 0xC10
|
||||
#define HW_PINCTRL_IRQSTAT2 0xC20
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* STMP POWER Register Definitions
|
||||
* stmp378x: POWER register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
|
|
@ -18,15 +18,46 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_POWER
|
||||
#define _MACH_REGS_POWER
|
||||
|
||||
#ifndef __ARCH_ARM___POWER_H
|
||||
#define __ARCH_ARM___POWER_H 1
|
||||
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
|
||||
#define REGS_POWER_PHYS 0x80044000
|
||||
#define REGS_POWER_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_POWER_CTRL 0x0
|
||||
#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
|
||||
#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
|
||||
#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
|
||||
#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
|
||||
#define BM_POWER_CTRL_CLKGATE 0x40000000
|
||||
|
||||
#define REGS_POWER_BASE (void __iomem *)(REGS_BASE + 0x44000)
|
||||
#define REGS_POWER_BASE_PHYS (0x80044000)
|
||||
#define REGS_POWER_SIZE 0x00002000
|
||||
HW_REGISTER(HW_POWER_MINPWR, REGS_POWER_BASE, 0x00000020)
|
||||
HW_REGISTER(HW_POWER_CHARGE, REGS_POWER_BASE, 0x00000030)
|
||||
#endif /* __ARCH_ARM___POWER_H */
|
||||
#define HW_POWER_5VCTRL 0x10
|
||||
#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
|
||||
|
||||
#define HW_POWER_MINPWR 0x20
|
||||
|
||||
#define HW_POWER_CHARGE 0x30
|
||||
|
||||
#define HW_POWER_VDDDCTRL 0x40
|
||||
|
||||
#define HW_POWER_VDDACTRL 0x50
|
||||
|
||||
#define HW_POWER_VDDIOCTRL 0x60
|
||||
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
|
||||
#define BP_POWER_VDDIOCTRL_TRG 0
|
||||
|
||||
#define HW_POWER_STS 0xC0
|
||||
#define BM_POWER_STS_VBUSVALID 0x00000002
|
||||
#define BM_POWER_STS_BVALID 0x00000004
|
||||
#define BM_POWER_STS_AVALID 0x00000008
|
||||
#define BM_POWER_STS_DC_OK 0x00000200
|
||||
|
||||
#define HW_POWER_RESET 0x100
|
||||
|
||||
#define HW_POWER_DEBUG 0x110
|
||||
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
|
||||
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
|
||||
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* STMP TIMROT Register Definitions
|
||||
* stmp378x: TIMROT register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
|
|
@ -18,199 +18,51 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_TIMROT
|
||||
#define _MACH_REGS_TIMROT
|
||||
|
||||
#ifndef __ARCH_ARM___TIMROT_H
|
||||
#define __ARCH_ARM___TIMROT_H 1
|
||||
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
|
||||
#define REGS_TIMROT_PHYS 0x80068000
|
||||
#define REGS_TIMROT_SIZE 0x2000
|
||||
|
||||
#include <mach/stmp3xxx_regs.h>
|
||||
#define HW_TIMROT_ROTCTRL 0x0
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_A 0
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_B 4
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
|
||||
#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
|
||||
#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
|
||||
#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
|
||||
#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
|
||||
#define BP_TIMROT_ROTCTRL_DIVIDER 16
|
||||
#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
|
||||
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
|
||||
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
|
||||
|
||||
#define REGS_TIMROT_BASE (REGS_BASE + 0x68000)
|
||||
#define REGS_TIMROT_BASE_PHYS (0x80068000)
|
||||
#define REGS_TIMROT_SIZE 0x00002000
|
||||
HW_REGISTER(HW_TIMROT_ROTCTRL, REGS_TIMROT_BASE, 0x00000000)
|
||||
#define HW_TIMROT_ROTCTRL_ADDR (REGS_TIMROT_BASE + 0x00000000)
|
||||
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
|
||||
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
|
||||
#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
|
||||
#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000
|
||||
#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000
|
||||
#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000
|
||||
#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000
|
||||
#define BP_TIMROT_ROTCTRL_STATE 22
|
||||
#define BM_TIMROT_ROTCTRL_STATE 0x01C00000
|
||||
#define BF_TIMROT_ROTCTRL_STATE(v) \
|
||||
(((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
|
||||
#define BP_TIMROT_ROTCTRL_DIVIDER 16
|
||||
#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
|
||||
#define BF_TIMROT_ROTCTRL_DIVIDER(v) \
|
||||
(((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
|
||||
#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
|
||||
#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
|
||||
#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
|
||||
#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \
|
||||
(((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
|
||||
#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
|
||||
#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
|
||||
#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
|
||||
#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_B 4
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
|
||||
#define BF_TIMROT_ROTCTRL_SELECT_B(v) \
|
||||
(((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_A 0
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
|
||||
#define BF_TIMROT_ROTCTRL_SELECT_A(v) \
|
||||
(((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6
|
||||
#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7
|
||||
HW_REGISTER_0(HW_TIMROT_ROTCOUNT, REGS_TIMROT_BASE, 0x00000010)
|
||||
#define HW_TIMROT_ROTCOUNT_ADDR (REGS_TIMROT_BASE + 0x00000010)
|
||||
#define BP_TIMROT_ROTCOUNT_UPDOWN 0
|
||||
#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
|
||||
#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \
|
||||
(((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
|
||||
/*
|
||||
* multi-register-define name HW_TIMROT_TIMCTRLn
|
||||
* base 0x00000020
|
||||
* count 3
|
||||
* offset 0x20
|
||||
*/
|
||||
HW_REGISTER_INDEXED(HW_TIMROT_TIMCTRLn, REGS_TIMROT_BASE, 0x00000020, 0x20)
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
|
||||
#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
|
||||
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
|
||||
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
|
||||
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
|
||||
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
|
||||
#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
|
||||
(((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
|
||||
#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
|
||||
#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
|
||||
#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
|
||||
#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
|
||||
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
||||
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
|
||||
#define BF_TIMROT_TIMCTRLn_SELECT(v) \
|
||||
(((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB
|
||||
#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC
|
||||
/*
|
||||
* multi-register-define name HW_TIMROT_TIMCOUNTn
|
||||
* base 0x00000030
|
||||
* count 3
|
||||
* offset 0x20
|
||||
*/
|
||||
HW_REGISTER_0_INDEXED(HW_TIMROT_TIMCOUNTn, REGS_TIMROT_BASE, 0x00000030,
|
||||
0x20)
|
||||
#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16
|
||||
#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000
|
||||
#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \
|
||||
(((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT)
|
||||
#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0
|
||||
#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF
|
||||
#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \
|
||||
(((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT)
|
||||
HW_REGISTER(HW_TIMROT_TIMCTRL3, REGS_TIMROT_BASE, 0x00000080)
|
||||
#define HW_TIMROT_TIMCTRL3_ADDR (REGS_TIMROT_BASE + 0x00000080)
|
||||
#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16
|
||||
#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000
|
||||
#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \
|
||||
(((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB
|
||||
#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC
|
||||
#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000
|
||||
#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000
|
||||
#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400
|
||||
#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200
|
||||
#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100
|
||||
#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080
|
||||
#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040
|
||||
#define BP_TIMROT_TIMCTRL3_PRESCALE 4
|
||||
#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030
|
||||
#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \
|
||||
(((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
|
||||
#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
|
||||
#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
|
||||
#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
|
||||
#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
|
||||
#define BP_TIMROT_TIMCTRL3_SELECT 0
|
||||
#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F
|
||||
#define BF_TIMROT_TIMCTRL3_SELECT(v) \
|
||||
(((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB
|
||||
#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC
|
||||
HW_REGISTER_0(HW_TIMROT_TIMCOUNT3, REGS_TIMROT_BASE, 0x00000090)
|
||||
#define HW_TIMROT_TIMCOUNT3_ADDR (REGS_TIMROT_BASE + 0x00000090)
|
||||
#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16
|
||||
#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000
|
||||
#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \
|
||||
(((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT)
|
||||
#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0
|
||||
#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF
|
||||
#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \
|
||||
(((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT)
|
||||
HW_REGISTER_0(HW_TIMROT_VERSION, REGS_TIMROT_BASE, 0x000000a0)
|
||||
#define HW_TIMROT_VERSION_ADDR (REGS_TIMROT_BASE + 0x000000a0)
|
||||
#define BP_TIMROT_VERSION_MAJOR 24
|
||||
#define BM_TIMROT_VERSION_MAJOR 0xFF000000
|
||||
#define BF_TIMROT_VERSION_MAJOR(v) \
|
||||
(((v) << 24) & BM_TIMROT_VERSION_MAJOR)
|
||||
#define BP_TIMROT_VERSION_MINOR 16
|
||||
#define BM_TIMROT_VERSION_MINOR 0x00FF0000
|
||||
#define BF_TIMROT_VERSION_MINOR(v) \
|
||||
(((v) << 16) & BM_TIMROT_VERSION_MINOR)
|
||||
#define BP_TIMROT_VERSION_STEP 0
|
||||
#define BM_TIMROT_VERSION_STEP 0x0000FFFF
|
||||
#define BF_TIMROT_VERSION_STEP(v) \
|
||||
(((v) << 0) & BM_TIMROT_VERSION_STEP)
|
||||
#endif /* __ARCH_ARM___TIMROT_H */
|
||||
#define HW_TIMROT_ROTCOUNT 0x10
|
||||
#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
|
||||
#define BP_TIMROT_ROTCOUNT_UPDOWN 0
|
||||
|
||||
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCTRLn 0x20
|
||||
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
|
||||
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
||||
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
|
||||
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
|
||||
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
|
||||
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
|
||||
|
||||
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCOUNTn 0x30
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Reference in a new issue