dect: com-on-air: device driver core
Add the chip-specific parts of the com-on-air driver. Signed-off-by: Patrick McHardy <kaber@trash.net>
This commit is contained in:
parent
28c157ecb4
commit
dfdc90c521
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@ -40,6 +40,8 @@ source "drivers/net/Kconfig"
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source "drivers/isdn/Kconfig"
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source "drivers/dect/Kconfig"
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source "drivers/telephony/Kconfig"
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# input before char - char/joystick depends on it. As does USB.
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@ -82,6 +82,7 @@ obj-$(CONFIG_MD) += md/
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obj-$(CONFIG_BT) += bluetooth/
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obj-$(CONFIG_ACCESSIBILITY) += accessibility/
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obj-$(CONFIG_ISDN) += isdn/
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obj-$(CONFIG_DECT) += dect/
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obj-$(CONFIG_EDAC) += edac/
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obj-$(CONFIG_MCA) += mca/
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obj-$(CONFIG_EISA) += eisa/
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@ -0,0 +1,10 @@
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menuconfig DECTDEVICES
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bool "DECT device support"
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help
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Say Y here to show DECT device driver options.
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if DECTDEVICES
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source "drivers/dect/coa/Kconfig"
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endif
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@ -0,0 +1 @@
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obj-$(CONFIG_DECT_COA) += coa/
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@ -0,0 +1,2 @@
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config DECT_COA
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tristate
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@ -0,0 +1,3 @@
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com_on_air-objs := sc14421_firmware.o sc14421.o
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obj-$(CONFIG_DECT_COA) += com_on_air.o
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@ -0,0 +1,76 @@
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/*
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* com_on_air - basic driver for the Dosch and Amand "com on air" cards
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* authors:
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* (C) 2008 Andreas Schuler <krater at badterrorist dot com>
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* (C) 2008 Matthias Wenzel <dect at mazzoo dot de>
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* (C) 2009 Patrick McHardy <kaber@trash.net>
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*
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*/
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#ifndef COM_ON_AIR_H
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#define COM_ON_AIR_H
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#include <linux/types.h>
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struct coa_freq_map_entry {
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struct {
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u8 divisor;
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u8 swcnt;
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} rx, tx;
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};
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struct coa_freq_map {
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struct coa_freq_map_entry carrier[DECT_CARRIER_NUM];
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};
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struct coa_device;
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struct coa_radio_ops {
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void (*rx_init)(const struct coa_device *dev, u16 offset);
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void (*tx_init)(const struct coa_device *dev, u16 offset);
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void (*set_carrier)(const struct coa_device *dev, u16 offset,
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enum dect_slot_states mode, u8 carrier);
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u64 (*map_band)(struct coa_device *dev,
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const struct dect_band *band);
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const char *type;
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};
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enum coa_device_types {
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COA_TYPE_PCI,
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COA_TYPE_PCMCIA,
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};
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struct coa_device {
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const struct device *dev;
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unsigned int irq;
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enum coa_device_types type;
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const struct coa_radio_ops *radio_ops;
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struct coa_freq_map freq_map;
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uint config_base;
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u8 __iomem *sc14421_base;
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u16 cfg_reg;
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u16 irq_reg;
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u16 code_base;
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u16 data_base;
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u16 data_mask;
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u8 ctrl;
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};
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extern irqreturn_t sc14421_interrupt(int irq, void *dev_id);
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extern const struct dect_transceiver_ops sc14421_transceiver_ops;
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extern int sc14421_init_device(struct coa_device *dev);
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extern void sc14421_shutdown_device(struct coa_device *dev);
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extern void sc14421_rfdesc_write(const struct coa_device *dev, u16 offset,
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const u8 *src, u16 length);
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#endif
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@ -0,0 +1,157 @@
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/*
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* com_on_air - basic driver for the Dosch and Amand "com on air" cards
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* authors:
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* (C) 2008 Andreas Schuler <krater at badterrorist dot com>
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* (C) 2008 Matthias Wenzel <dect at mazzoo dot de>
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*
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*/
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#ifndef DIP_OPCODE_H
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#define DIP_OPCODE_H
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#define BR 0x01
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#define JMP 0x02
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#define JMP1 0x03
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#define RTN 0x04
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#define BK_A1 0x05
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#define WNTM1 0x06
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#define WNTP1 0x07
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#define WNT 0x08
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#define WT 0x09
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#define RFDIS 0x0a
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#define RFEN 0x0b
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#define LD_PTR 0x0c
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#define SLOTZERO 0x0d
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#define BK_A 0x0e
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#define BK_C 0x0f
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#define B_RST 0x20
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#define B_ST2 0x21
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#define B_XT 0x24
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#define B_BT2 0x25
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#define B_BTFU 0x25
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#define B_XOFF 0x26
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#define B_ON 0x27
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#define B_XON 0x27
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#define UNLCK 0x28
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#define B_SR 0x29
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#define B_XR 0x2b
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#define EN_SL_ADJ 0x2c
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#define B_BR2 0x2d
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#define B_BRFU 0x2d
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#define B_RINV 0x2e
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#define B_RON 0x2f
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#define B_ST 0x31
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#define B_TX 0x31
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#define B_AT 0x32
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#define B_RC 0x33
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#define B_BT 0x34
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#define B_BTFP 0x35
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#define B_BTP 0x35
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#define B_AT2 0x37
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#define B_WRS 0x39
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#define B_AR 0x3a
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#define B_BR 0x3c
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#define B_BRP 0x3d
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#define B_BRFP 0x3d
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#define B_AR2 0x3f
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#define D_RST 0x40
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#define D_ON 0x42
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#define D_OFF 0x43
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#define D_PREP 0x44
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#define WSC 0x48
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#define D_LDK 0x50
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#define D_LDS 0x57
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#define D_WRS 0x5f
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#define U_PSC 0x60
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#define U_INT0 0x61
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#define RCK_INT 0x62
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#define RCK_EXT 0x63
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#define B_WB_OFF 0x64
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#define B_WB_ON 0x65
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#define CLK1 0x66
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#define CLK3 0x67
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#define U_CK8 0x68
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#define U_CK4 0x69
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#define U_CK2 0x6a
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#define U_INT1 0x6b
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#define U_CK1 0x6c
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#define U_INT2 0x6d
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#define U_INT3 0x6f
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#define A_RCV0 0x80
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#define A_RCV36 0x82
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#define A_RCV30 0x83
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#define A_RCV24 0x84
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#define A_RCV18 0x85
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#define A_RCV12 0x86
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#define A_RCV6 0x87
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#define A_RCV33 0x8a
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#define A_RCV27 0x8b
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#define A_RCV21 0x8c
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#define A_RCV15 0x8d
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#define A_RCV9 0x8e
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#define A_RCV3 0x8f
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#define MEN3N 0xa2
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#define MEN3 0xa3
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#define MEN1N 0xa4
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#define MEN1 0xa5
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#define MEN2N 0xa6
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#define MEN2 0xa7
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#define M_RD 0xa8
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#define M_RST 0xa9
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#define M_WRS 0xb8
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#define M_WR 0xb9
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#define A_RST 0xc0
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#define A_MUTE 0xc1
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#define A_STOFF 0xc2
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#define A_ALAW 0xc3
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#define A_DT 0xc4
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#define A_NORM 0xc5
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#define A_LDR 0xc6
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#define A_LDW 0xc7
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#define A_LIN 0xc8
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#define A_MTOFF 0xc9
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#define A_MUTE1 0xca
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#define A_MTOFF1 0xcb
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#define A_STON 0xcc
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#define A_DT1 0xcd
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#define A_LDR1 0xce
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#define A_LDW1 0xcf
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#define A_STRN 0xe0
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#define P_LD 0xe8
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#define P_EN 0xe9
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#define P_SC 0xea
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#define A_RST1 0xeb
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#define P_LDL 0xec
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#define P_LDH 0xed
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#define C_ON 0xee
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#define C_OFF 0xef
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#define C_LD 0xfa
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#endif
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@ -0,0 +1,724 @@
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/*
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* com_on_air - basic driver for the Dosch and Amand "com on air" cards
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* authors:
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* (C) 2008 Andreas Schuler <krater at badterrorist dot com>
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* (C) 2008 Matthias Wenzel <dect at mazzoo dot de>
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* (C) 2009 Patrick McHardy <kaber@trash.net>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/skbuff.h>
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#include <linux/dect.h>
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#include <net/dect/dect.h>
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#include <net/dect/mac_csf.h>
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#include <net/dect/transceiver.h>
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#include <asm/io.h>
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#include "com_on_air.h"
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#include "sc14421_firmware.h"
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#include "dip_opcodes.h"
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/*
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* The com-on-air devices contain a 2k data RAM and 512b code RAM. The address
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* space is layed out as follows:
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*
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* PCI - size 8k:
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*
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* 0x0a00 - 0x11ff: data memory
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* 0x1a00 - 0x1bff: code memory
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* 0x1f00 - 0x1fff: DIP control and status registers
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*
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* PCMCIA - size 1k:
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*
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* 0x0000 - 0x01ff: 256 bytes memory
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* 0x0200 - 0x02ff: DIP control and status registers
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*
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* Memory of the PCMCIA device is addressed in 16 bit little endian quantities.
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* To access data or code memory, the corresponding bank needs to be mapped
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* into the memory window.
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*
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* The first bank of the data memory contains DIP specific control data,
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* the remaining banks are used to store packet and slot configuration data.
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*/
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#define SC14421_DIPSTOPPED 0x80
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#define SC14421_RAMBANK0 0x00
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#define SC14421_RAMBANK1 0x04
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#define SC14421_RAMBANK2 0x08
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#define SC14421_RAMBANK3 0x0c
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#define SC14421_RAMBANK4 0x10
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#define SC14421_RAMBANK5 0x14
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#define SC14421_RAMBANK6 0x18
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#define SC14421_RAMBANK7 0x1c
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#define SC14421_CODEBANK 0x20
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#define SC14421_BANKSIZE 0x100
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/* Interrupts 0-3 */
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#define SC14421_IRQ_SLOT_0_5 0x01
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#define SC14421_IRQ_SLOT_6_11 0x02
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#define SC14421_IRQ_SLOT_12_17 0x04
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#define SC14421_IRQ_SLOT_18_23 0x08
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#define SC14421_IRQ_MASK 0x0f
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/*
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* Burst Mode Controller control information
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*/
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/* Maximum number of unmasked errors in S-field bits 8 to 31 */
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#define SC14421_BC0_S_ERR_SHIFT 4
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/* Invert incoming data (RDI) */
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#define SC14421_BC0_INV_RDI 0x08
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/* Invert outgoing data (TDO) */
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#define SC14421_BC0_INV_TDO 0x04
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/* Disable writing B-field on A-field CRC error */
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#define SC14421_BC0_SENS_A 0x02
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/* PP/FP mode */
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#define SC14421_BC0_PP_MODE 0x01
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/* Error test mask for S-field bits 15-8 */
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#define SC14421_BC1_MASK_MASK 0xff
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/* Sliding error test mask for S-field bits 15-8 */
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#define SC14421_BC2_SLIDE_MASK 0xff
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/* DAC output value when BCM is active (for frequency control?) */
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#define SC14421_BC3_DAC_MASK 0x1f
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/* Only perform phase jump for correct A-field CRC + SL_EN_ADJ command */
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#define SC14421_BC4_ADP 0x10
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/* Window in which S-field is accepted */
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#define SC14421_BC4_WIN_MASK 0x0f
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/* Amplitude-trimming of gaussian shape */
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#define SC14421_BC5_VOL_SHIFT 4
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/* Disable scrambling */
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#define SC14421_BC5_SC_OFF 0x08
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/* PD1 synchronization pattern:
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* 0 = S-field received, 1 = preamble + first 2 bits of synchronization word */
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#define SC14421_BC5_DO_FR 0x04
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/* TDO output shape */
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#define SC14421_BC5_TDO_DIGITAL 0x00
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#define SC14421_BC5_TDO_GAUSIAN 0x01
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#define SC14421_BC5_TDO_POWER_DOWN 0x02
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#define SC14421_BC5_TDO_MID_LEVEL 0x03
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/* Low 4 bits of multiframe number */
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#define SC14421_BC6_MFR_SHIFT 4
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#define SC14421_BC6_MFR_MASK 0xf0
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/* Frame number */
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#define SC14421_BC6_FR_MASK 0x0f
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/*
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* Burst Mode Controller status information
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*/
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/* Peak binary value of ADC (RSSI) */
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#define SC14421_ST0_ADC_MASK 0x3f
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/* S-pattern recognized according to BMC configuration */
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#define SC14421_ST1_IN_SYNC 0x80
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/* A-field R-CRC correct */
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#define SC14421_ST1_A_CRC 0x40
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/* Protected Bn-subfield R-CRC correct */
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#define SC14421_ST1_B_CRC_MASK 0x3c
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#define SC14421_ST1_B1_CRC 0x20
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#define SC14421_ST1_B2_CRC 0x10
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#define SC14421_ST1_B3_CRC 0x08
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#define SC14421_ST1_B4_CRC 0x04
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/* B-field X-CRC correct */
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#define SC14421_ST1_X_CRC 0x02
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/* Z-field equals X-CRC */
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#define SC14421_ST1_Z_CRC 0x01
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/* Phase offset of received S-field: which of the nine internal clock cycles
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* per symbol sampled the incoming data. The frequency deviation can be
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* calculated from the difference of the offsets of two consequitive frames as:
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*
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* K * (T / 9) / 10m = K * 96ns / 10m = K * 9.6ppm
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*/
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#define SC14421_ST2_TAP_SHIFT 4
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#define SC14421_ST2_TAP_MASK 0xf0
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/* Number of unmasked S-field errors according to BMC configuration */
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#define SC14421_ST2_S_ERR_SHIFT 0
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#define SC14421_ST2_S_ERR_MASK 0x0f
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/* Phase offset of received S-field. */
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#define SC14421_ST3_PHASE_MASK 0xff
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/* DC offset of received data to comparator reference input (DAC) */
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#define SC14421_ST4_DC_MASK 0x3f
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static const u8 banktable[] = {
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SC14421_RAMBANK1, 0,
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SC14421_RAMBANK1, 0,
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SC14421_RAMBANK2, 0,
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SC14421_RAMBANK2, 0,
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SC14421_RAMBANK3, 0,
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SC14421_RAMBANK3, 0,
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SC14421_RAMBANK4, 0,
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SC14421_RAMBANK4, 0,
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SC14421_RAMBANK5, 0,
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SC14421_RAMBANK5, 0,
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SC14421_RAMBANK6, 0,
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SC14421_RAMBANK6, 0,
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};
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static const u8 jumptable[] = {
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JP0, 0,
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JP2, 0,
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JP4, 0,
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JP6, 0,
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JP8, 0,
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JP10, 0,
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JP12, 0,
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JP14, 0,
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JP16, 0,
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JP18, 0,
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JP20, 0,
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JP22, 0
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};
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static const u8 patchtable[] = {
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PP0, 0,
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PP2, 0,
|
||||
PP4, 0,
|
||||
PP6, 0,
|
||||
PP8, 0,
|
||||
PP10, 0,
|
||||
PP12, 0,
|
||||
PP14, 0,
|
||||
PP16, 0,
|
||||
PP18, 0,
|
||||
PP20, 0,
|
||||
PP22, 0
|
||||
};
|
||||
|
||||
static const u8 sc14421_rx_funcs[DECT_PACKET_MAX + 1][DECT_B_MAX + 1] = {
|
||||
[DECT_PACKET_P00][DECT_B_NONE] = RecvP32U,
|
||||
[DECT_PACKET_P32][DECT_B_UNPROTECTED] = RecvP32U,
|
||||
[DECT_PACKET_P32][DECT_B_PROTECTED] = RecvP32P,
|
||||
};
|
||||
|
||||
static const u8 sc14421_tx_funcs[DECT_PACKET_MAX + 1][DECT_B_MAX + 1] = {
|
||||
[DECT_PACKET_P00][DECT_B_NONE] = TransmitP00,
|
||||
[DECT_PACKET_P32][DECT_B_UNPROTECTED] = TransmitP32U,
|
||||
[DECT_PACKET_P32][DECT_B_PROTECTED] = TransmitP32P,
|
||||
};
|
||||
|
||||
/*
|
||||
* Raw IO functions
|
||||
*/
|
||||
static u8 sc14421_read(const struct coa_device *dev, u16 offset)
|
||||
{
|
||||
switch (dev->type) {
|
||||
case COA_TYPE_PCI:
|
||||
return readb(dev->sc14421_base + offset);
|
||||
case COA_TYPE_PCMCIA:
|
||||
return le16_to_cpu(readw(dev->sc14421_base + 2 * offset));
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
static void sc14421_write(const struct coa_device *dev, u16 offset, u8 value)
|
||||
{
|
||||
switch (dev->type) {
|
||||
case COA_TYPE_PCI:
|
||||
writeb(value, dev->sc14421_base + offset);
|
||||
break;
|
||||
case COA_TYPE_PCMCIA:
|
||||
writew(cpu_to_le16(value), dev->sc14421_base + 2 * offset);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void sc14421_stop_dip(struct coa_device *dev)
|
||||
{
|
||||
/* Prevent the interrupt handler from restarting the DIP */
|
||||
dev->ctrl = SC14421_DIPSTOPPED;
|
||||
|
||||
/* Stop the DIP and wait for interrupt handler to complete */
|
||||
sc14421_write(dev, dev->cfg_reg, SC14421_DIPSTOPPED);
|
||||
synchronize_irq(dev->irq);
|
||||
}
|
||||
|
||||
static void sc14421_start_dip(struct coa_device *dev)
|
||||
{
|
||||
dev->ctrl = 0;
|
||||
sc14421_write(dev, dev->cfg_reg, 0x00);
|
||||
}
|
||||
|
||||
static void sc14421_switch_to_bank(const struct coa_device *dev, u8 bank)
|
||||
{
|
||||
if (dev->type != COA_TYPE_PCMCIA)
|
||||
return;
|
||||
sc14421_write(dev, dev->cfg_reg, bank | dev->ctrl);
|
||||
/* need to wait for 4 IO cycles */
|
||||
inb_p(dev->config_base);
|
||||
inb_p(dev->config_base);
|
||||
inb_p(dev->config_base);
|
||||
inb_p(dev->config_base);
|
||||
}
|
||||
|
||||
/*
|
||||
* Code memory IO functions
|
||||
*/
|
||||
static void sc14421_write_cmd(const struct coa_device *dev, u16 label,
|
||||
u8 opcode, u8 operand)
|
||||
{
|
||||
sc14421_write(dev, dev->code_base + 2 * label + 0, opcode);
|
||||
sc14421_write(dev, dev->code_base + 2 * label + 1, operand);
|
||||
}
|
||||
|
||||
static void sc14421_to_cmem(const struct coa_device *dev,
|
||||
const u8 *src, u16 length)
|
||||
{
|
||||
u16 i;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
sc14421_write(dev, dev->code_base + i, src[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Data memory IO functions
|
||||
*/
|
||||
static inline u8 sc14421_dread(const struct coa_device *dev, u16 offset)
|
||||
{
|
||||
return sc14421_read(dev, dev->data_base + (offset & dev->data_mask));
|
||||
}
|
||||
|
||||
static inline void sc14421_dwrite(const struct coa_device *dev,
|
||||
u16 offset, u8 value)
|
||||
{
|
||||
sc14421_write(dev, dev->data_base + (offset & dev->data_mask), value);
|
||||
}
|
||||
|
||||
static void sc14421_to_dmem(const struct coa_device *dev, u16 offset,
|
||||
const u8 *src, u16 length)
|
||||
{
|
||||
u16 i;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
sc14421_dwrite(dev, offset + i, src[i]);
|
||||
}
|
||||
|
||||
static void sc14421_from_dmem(const struct coa_device *dev, u8 *dst,
|
||||
u16 offset, u16 length)
|
||||
{
|
||||
u16 i;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
dst[i] = sc14421_dread(dev, offset + i);
|
||||
}
|
||||
|
||||
static u16 sc14421_slot_offset(u8 slot)
|
||||
{
|
||||
u16 offset;
|
||||
|
||||
offset = SC14421_BANKSIZE + slot / 4 * SC14421_BANKSIZE;
|
||||
if (slot & 0x2)
|
||||
offset += SC14421_BANKSIZE / 2;
|
||||
return offset;
|
||||
}
|
||||
|
||||
void sc14421_rfdesc_write(const struct coa_device *dev, u16 offset,
|
||||
const u8 *src, u16 length)
|
||||
{
|
||||
sc14421_to_dmem(dev, offset + RF_DESC, src, length);
|
||||
}
|
||||
|
||||
/*
|
||||
* Transceiver operations
|
||||
*/
|
||||
|
||||
static void sc14421_disable(const struct dect_transceiver *trx)
|
||||
{
|
||||
sc14421_stop_dip(dect_transceiver_priv(trx));
|
||||
}
|
||||
|
||||
static void sc14421_enable(const struct dect_transceiver *trx)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
u8 slot;
|
||||
|
||||
/* Restore slot table to a pristine state */
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
|
||||
sc14421_write_cmd(dev, patchtable[slot], WNT, 2);
|
||||
|
||||
if (trx->mode == DECT_TRANSCEIVER_MASTER)
|
||||
sc14421_write_cmd(dev, RFStart, BR, SlotTable);
|
||||
else {
|
||||
sc14421_write_cmd(dev, RFStart, BR, SyncInit);
|
||||
sc14421_write_cmd(dev, SyncLoop, BR, Sync);
|
||||
}
|
||||
|
||||
sc14421_start_dip(dect_transceiver_priv(trx));
|
||||
}
|
||||
|
||||
static void sc14421_confirm(const struct dect_transceiver *trx)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
|
||||
/*
|
||||
* This locks the firmware into a cycle where it will receive every
|
||||
* 24th slot. This must happen within the time it takes to transmit
|
||||
* 22 slots after the interrupt to lock to the correct signal.
|
||||
*/
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, SyncLoop, BR, SyncLock);
|
||||
}
|
||||
|
||||
static void sc14421_unlock(const struct dect_transceiver *trx)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
|
||||
/* Restore jump into Sync loop */
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, SyncLoop, BR, Sync);
|
||||
}
|
||||
|
||||
static void sc14421_lock(const struct dect_transceiver *trx, u8 slot)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
|
||||
/*
|
||||
* We're receiving the single slot "slot". Adjust the firmware so it
|
||||
* will jump into the correct slottable position on the next receive
|
||||
* event. This will automagically establish the correct slot numbers
|
||||
* and thereby interrupt timing for all slots.
|
||||
*/
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, SyncLoop, BR, jumptable[slot]);
|
||||
}
|
||||
|
||||
static void sc14421_set_mode(const struct dect_transceiver *trx,
|
||||
const struct dect_channel_desc *chd,
|
||||
enum dect_slot_states mode)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
u8 slot = chd->slot;
|
||||
u16 off;
|
||||
|
||||
switch (mode) {
|
||||
case DECT_SLOT_IDLE:
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, patchtable[slot], WNT, 2);
|
||||
break;
|
||||
case DECT_SLOT_SCANNING:
|
||||
case DECT_SLOT_RX:
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
dev->radio_ops->rx_init(dev, off);
|
||||
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, patchtable[slot], JMP,
|
||||
sc14421_rx_funcs[chd->pkt][chd->b_fmt]);
|
||||
break;
|
||||
case DECT_SLOT_TX:
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
dev->radio_ops->tx_init(dev, off);
|
||||
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_write_cmd(dev, patchtable[slot], JMP,
|
||||
sc14421_tx_funcs[chd->pkt][chd->b_fmt]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void sc14421_set_carrier(const struct dect_transceiver *trx,
|
||||
u8 slot, u8 carrier)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
const struct dect_transceiver_slot *ts = &trx->slots[slot];
|
||||
u16 off;
|
||||
|
||||
WARN_ON(ts->state == DECT_SLOT_IDLE);
|
||||
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
dev->radio_ops->set_carrier(dev, off, ts->state, carrier);
|
||||
}
|
||||
|
||||
static u64 sc14421_set_band(const struct dect_transceiver *trx,
|
||||
const struct dect_band *band)
|
||||
{
|
||||
struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
|
||||
return dev->radio_ops->map_band(dev, band);
|
||||
}
|
||||
|
||||
static void sc14421_tx(const struct dect_transceiver *trx, struct sk_buff *skb)
|
||||
{
|
||||
const struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
u8 slot = DECT_TRX_CB(skb)->slot;
|
||||
u16 off;
|
||||
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
|
||||
sc14421_to_dmem(dev, off + SD_PREAMBLE_OFF,
|
||||
skb_mac_header(skb), skb->mac_len);
|
||||
sc14421_to_dmem(dev, off + SD_DATA_OFF, skb->data, skb->len);
|
||||
sc14421_dwrite(dev, off + TX_DESC + TRX_DESC_FN,
|
||||
DECT_TRX_CB(skb)->frame);
|
||||
|
||||
kfree_skb(skb);
|
||||
}
|
||||
|
||||
const struct dect_transceiver_ops sc14421_transceiver_ops = {
|
||||
.name = "sc14421",
|
||||
.slotmask = 0x555555,
|
||||
.eventrate = 6,
|
||||
.latency = 6,
|
||||
.disable = sc14421_disable,
|
||||
.enable = sc14421_enable,
|
||||
.confirm = sc14421_confirm,
|
||||
.unlock = sc14421_unlock,
|
||||
.lock = sc14421_lock,
|
||||
.set_mode = sc14421_set_mode,
|
||||
.set_carrier = sc14421_set_carrier,
|
||||
.set_band = sc14421_set_band,
|
||||
.tx = sc14421_tx,
|
||||
.destructor = dect_transceiver_free,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(sc14421_transceiver_ops);
|
||||
|
||||
static u8 sc14421_clear_interrupt(const struct coa_device *dev)
|
||||
{
|
||||
u8 int1, int2, cnt = 0;
|
||||
|
||||
int1 = sc14421_read(dev, dev->cfg_reg);
|
||||
/* is the card still plugged? */
|
||||
if (int1 == 0xff)
|
||||
return 0;
|
||||
|
||||
int2 = int1 & SC14421_IRQ_MASK;
|
||||
|
||||
/* Clear interrupt status before checking for any remaining events */
|
||||
if (int2 && dev->type == COA_TYPE_PCI)
|
||||
sc14421_write(dev, 0x1f02, 0x80);
|
||||
|
||||
while (int1) {
|
||||
cnt++;
|
||||
if (cnt > 254) {
|
||||
int2 = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
int1 = sc14421_read(dev, dev->cfg_reg) & SC14421_IRQ_MASK;
|
||||
int2 |= int1;
|
||||
}
|
||||
|
||||
return int2 & SC14421_IRQ_MASK;
|
||||
}
|
||||
|
||||
static void sc14421_process_slot(const struct coa_device *dev,
|
||||
struct dect_transceiver *trx,
|
||||
struct dect_transceiver_event *event,
|
||||
u8 slot)
|
||||
{
|
||||
struct dect_transceiver_slot *ts = &trx->slots[slot];
|
||||
struct sk_buff *skb;
|
||||
u16 off;
|
||||
u8 rssi;
|
||||
|
||||
if (ts->state == DECT_SLOT_IDLE || ts->state == DECT_SLOT_TX)
|
||||
return;
|
||||
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
|
||||
/*
|
||||
* The SC14421 contains a 6 bit ADC for RSSI measurement, convert to
|
||||
* units used by the stack.
|
||||
*/
|
||||
rssi = sc14421_dread(dev, off + SD_RSSI_OFF) * DECT_RSSI_RANGE / 63;
|
||||
|
||||
/* validate and clear checksum */
|
||||
if ((sc14421_dread(dev, off + SD_CSUM_OFF) & 0xc0) != 0xc0)
|
||||
goto out;
|
||||
sc14421_dwrite(dev, off + SD_CSUM_OFF, 0);
|
||||
|
||||
skb = dect_transceiver_alloc_skb(trx, slot);
|
||||
if (skb == NULL)
|
||||
goto out;
|
||||
sc14421_from_dmem(dev, skb->data, off + SD_DATA_OFF, skb->len);
|
||||
DECT_TRX_CB(skb)->rssi = rssi;
|
||||
__skb_queue_tail(&event->rx_queue, skb);
|
||||
|
||||
ts->rx_bytes += skb->len;
|
||||
ts->rx_packets++;
|
||||
out:
|
||||
ts->rssi = dect_average_rssi(ts->rssi, rssi);
|
||||
dect_transceiver_record_rssi(event, slot, rssi);
|
||||
|
||||
/* Update frame number for next reception */
|
||||
sc14421_dwrite(dev, off + RX_DESC + TRX_DESC_FN,
|
||||
dect_next_framenum(trx->cell->timer_base[DECT_TIMER_RX].framenum));
|
||||
}
|
||||
|
||||
irqreturn_t sc14421_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct dect_transceiver *trx = dev_id;
|
||||
struct coa_device *dev = dect_transceiver_priv(trx);
|
||||
struct dect_transceiver_event *event;
|
||||
u8 slot, i;
|
||||
|
||||
irq = sc14421_clear_interrupt(dev);
|
||||
if (!irq)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (unlikely(hweight8(irq) != 1))
|
||||
dev_info(dev->dev, "lost some interrupts\n");
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!(irq & (1 << i)))
|
||||
continue;
|
||||
|
||||
event = dect_transceiver_event(trx, i % 2, i * 6);
|
||||
if (event == NULL)
|
||||
goto out;
|
||||
|
||||
for (slot = 6 * i; slot < 6 * (i + 1); slot += 2)
|
||||
sc14421_process_slot(dev, trx, event, slot);
|
||||
|
||||
dect_transceiver_queue_event(trx, event);
|
||||
}
|
||||
out:
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sc14421_interrupt);
|
||||
|
||||
static void sc14421_write_bmc_config(const struct coa_device *dev,
|
||||
u16 off, bool pp, bool tx)
|
||||
{
|
||||
u8 cfg;
|
||||
|
||||
cfg = 2 << SC14421_BC0_S_ERR_SHIFT;
|
||||
cfg |= SC14421_BC0_INV_TDO;
|
||||
cfg |= SC14421_BC0_SENS_A;
|
||||
if (pp && !tx)
|
||||
cfg |= SC14421_BC0_PP_MODE;
|
||||
sc14421_dwrite(dev, off + 0, cfg);
|
||||
|
||||
/* S-field error mask */
|
||||
sc14421_dwrite(dev, off + 1, 0);
|
||||
/* S-field sliding window error mask */
|
||||
sc14421_dwrite(dev, off + 2, 0x3f);
|
||||
|
||||
/* DAC output */
|
||||
sc14421_dwrite(dev, off + 3, 0);
|
||||
|
||||
cfg = SC14421_BC4_ADP;
|
||||
cfg |= 0xf;
|
||||
cfg |= 0x80;
|
||||
sc14421_dwrite(dev, off + 4, cfg);
|
||||
|
||||
cfg = SC14421_BC5_DO_FR;
|
||||
cfg |= tx ? SC14421_BC5_TDO_DIGITAL : SC14421_BC5_TDO_POWER_DOWN;
|
||||
sc14421_dwrite(dev, off + 5, cfg);
|
||||
|
||||
/* Frame number */
|
||||
sc14421_dwrite(dev, off + 6, 0);
|
||||
}
|
||||
|
||||
static void sc14421_init_slot(const struct coa_device *dev, u8 slot)
|
||||
{
|
||||
u16 off;
|
||||
|
||||
sc14421_switch_to_bank(dev, banktable[slot]);
|
||||
off = sc14421_slot_offset(slot);
|
||||
sc14421_write_bmc_config(dev, off + TX_DESC, slot < 12, true);
|
||||
sc14421_write_bmc_config(dev, off + RX_DESC, slot < 12, false);
|
||||
dev->radio_ops->rx_init(dev, off);
|
||||
}
|
||||
|
||||
static int sc14421_check_dram(const struct coa_device *dev)
|
||||
{
|
||||
unsigned int bank, i;
|
||||
unsigned int cnt;
|
||||
u16 off;
|
||||
u8 val;
|
||||
|
||||
for (bank = 0; bank < 8; bank++) {
|
||||
sc14421_switch_to_bank(dev, 4 * bank);
|
||||
|
||||
off = bank * SC14421_BANKSIZE;
|
||||
for (i = 0; i < SC14421_BANKSIZE - 2; i++)
|
||||
sc14421_dwrite(dev, off + i, bank + i);
|
||||
}
|
||||
|
||||
cnt = 0;
|
||||
for (bank = 0; bank < 8; bank++) {
|
||||
sc14421_switch_to_bank(dev, 4 * bank);
|
||||
|
||||
off = bank * SC14421_BANKSIZE;
|
||||
for (i = 0; i < SC14421_BANKSIZE - 2; i++) {
|
||||
val = sc14421_dread(dev, off + i);
|
||||
if (val != ((bank + i) & 0xff)) {
|
||||
dev_err(dev->dev,
|
||||
"memory error bank %.2x offset %.2x: "
|
||||
"%.2x != %.2x\n", bank, i,
|
||||
val, (bank + i) & 0xff);
|
||||
cnt++;
|
||||
}
|
||||
sc14421_dwrite(dev, off + i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt > 0)
|
||||
dev_err(dev->dev, "found %u memory r/w errors\n", cnt);
|
||||
return cnt ? -1 : 0;
|
||||
}
|
||||
|
||||
int sc14421_init_device(struct coa_device *dev)
|
||||
{
|
||||
u8 slot;
|
||||
|
||||
dev->ctrl = SC14421_DIPSTOPPED;
|
||||
|
||||
if (sc14421_check_dram(dev) < 0)
|
||||
return -EIO;
|
||||
|
||||
dev_info(dev->dev, "Loading firmware ...\n");
|
||||
sc14421_switch_to_bank(dev, SC14421_CODEBANK);
|
||||
sc14421_to_cmem(dev, sc14421_firmware, sizeof(sc14421_firmware));
|
||||
|
||||
sc14421_clear_interrupt(dev);
|
||||
|
||||
/* Init DIP */
|
||||
sc14421_switch_to_bank(dev, SC14421_RAMBANK0);
|
||||
sc14421_write_bmc_config(dev, DIP_RF_INIT, false, false);
|
||||
for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
|
||||
sc14421_init_slot(dev, slot);
|
||||
|
||||
/* Enable interrupts */
|
||||
if (dev->type == COA_TYPE_PCI)
|
||||
sc14421_write(dev, 0x1f06, 0x70);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sc14421_init_device);
|
||||
|
||||
void sc14421_shutdown_device(struct coa_device *dev)
|
||||
{
|
||||
sc14421_stop_dip(dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sc14421_shutdown_device);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* automatically generated file
|
||||
* DO NOT EDIT
|
||||
* edit firmware/filename.asm instead
|
||||
*/
|
||||
|
||||
#include "sc14421_firmware.h"
|
||||
|
||||
const unsigned char sc14421_firmware[] = {
|
||||
0x01, 0x01, 0x01, 0xc3, 0x0d, 0x00, 0x0f, 0x20,
|
||||
0x08, 0x02, 0x0f, 0x30, 0x08, 0x02, 0x0f, 0x40,
|
||||
0x08, 0x02, 0x61, 0x00, 0x0f, 0x50, 0x08, 0x02,
|
||||
0x0f, 0x60, 0x08, 0x02, 0x0f, 0x70, 0x08, 0x02,
|
||||
0x6b, 0x00, 0x0f, 0x80, 0x08, 0x02, 0x0f, 0x90,
|
||||
0x08, 0x02, 0x0f, 0xa0, 0x08, 0x02, 0x6d, 0x00,
|
||||
0x0f, 0xb0, 0x08, 0x02, 0x0f, 0xc0, 0x08, 0x02,
|
||||
0x0f, 0xd0, 0x08, 0x02, 0x6f, 0x00, 0x01, 0x02,
|
||||
0x02, 0x86, 0x02, 0x40, 0x09, 0x01, 0x2d, 0x0e,
|
||||
0x02, 0x50, 0x01, 0x36, 0x02, 0x86, 0x02, 0x40,
|
||||
0x01, 0x75, 0x02, 0x86, 0x02, 0x55, 0x02, 0x64,
|
||||
0x01, 0x38, 0x02, 0x86, 0x02, 0x55, 0x09, 0x01,
|
||||
0x25, 0x0e, 0x02, 0x61, 0x01, 0x39, 0x02, 0x86,
|
||||
0x02, 0x55, 0x01, 0x7e, 0x39, 0x00, 0x09, 0x06,
|
||||
0x20, 0x00, 0xec, 0x50, 0x09, 0x05, 0x08, 0x01,
|
||||
0x04, 0x00, 0x20, 0x00, 0xec, 0x50, 0x04, 0x00,
|
||||
0xed, 0x40, 0xec, 0x01, 0x09, 0x19, 0x08, 0x01,
|
||||
0x09, 0x09, 0x27, 0x00, 0xed, 0x02, 0x09, 0x05,
|
||||
0x29, 0x00, 0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02,
|
||||
0x09, 0x21, 0x3f, 0x06, 0x09, 0x3d, 0x04, 0x00,
|
||||
0x09, 0xf9, 0x09, 0x4f, 0xed, 0x01, 0xec, 0x40,
|
||||
0x04, 0x00, 0xed, 0x00, 0x09, 0x28, 0x20, 0x00,
|
||||
0x33, 0x50, 0x08, 0x01, 0x31, 0x00, 0x09, 0x01,
|
||||
0xed, 0x10, 0x09, 0x25, 0x37, 0x06, 0x09, 0x3d,
|
||||
0x04, 0x00, 0x09, 0xf9, 0x09, 0x54, 0x20, 0x00,
|
||||
0xec, 0x10, 0x09, 0x08, 0xec, 0x00, 0x04, 0x00,
|
||||
0x27, 0x00, 0x09, 0x0f, 0x26, 0x00, 0x09, 0x3d,
|
||||
0x04, 0x00, 0x09, 0x3d, 0x02, 0x68, 0x02, 0x68,
|
||||
0x02, 0x68, 0x09, 0x01, 0x27, 0x00, 0x09, 0x0b,
|
||||
0x04, 0x00, 0x3d, 0x0e, 0x02, 0x6d, 0x09, 0x03,
|
||||
0x2b, 0x00, 0x09, 0x06, 0x02, 0x52, 0x39, 0x00,
|
||||
0x09, 0x06, 0x01, 0x3d, 0x35, 0x0e, 0x02, 0x6d,
|
||||
0x09, 0x03, 0x24, 0x00, 0x09, 0x0d, 0x20, 0x00,
|
||||
0x02, 0x64, 0x01, 0x3d, 0x0b, 0x00, 0x09, 0x02,
|
||||
0xa4, 0x00, 0xb9, 0x4a, 0x09, 0x19, 0xa9, 0x00,
|
||||
0xa5, 0x00, 0xa4, 0x00, 0xb9, 0x4d, 0x09, 0x0a,
|
||||
0xa9, 0x00, 0xa5, 0x00, 0x09, 0x01, 0xec, 0x20,
|
||||
0x20, 0x00, 0x33, 0x58, 0x09, 0x08, 0xa7, 0x00,
|
||||
0x09, 0xb6, 0xa6, 0x00, 0xed, 0x00, 0x09, 0x10,
|
||||
0x04, 0x00, 0x50, 0x58, 0x09, 0x10, 0x50, 0x00,
|
||||
0x44, 0x00, 0x09, 0x27, 0x44, 0x00, 0x04, 0x00,
|
||||
0x5f, 0x00, 0x09, 0x0a, 0x5f, 0x00, 0x40, 0x00,
|
||||
0x04, 0x00, 0x57, 0x00, 0x09, 0x0a, 0x57, 0x00,
|
||||
0x04, 0x00, 0x40, 0x00, 0x0f, 0x20, 0x02, 0x86,
|
||||
0x09, 0xfa, 0xea, 0x20, 0xed, 0x42, 0x28, 0x00,
|
||||
0x09, 0x40, 0x26, 0x00, 0x29, 0x00, 0x08, 0x14,
|
||||
0x03, 0xbd, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
|
||||
0x01, 0xaf, 0x08, 0x17, 0xea, 0x00, 0x02, 0x20,
|
||||
0x61, 0x00, 0x08, 0x16, 0x01, 0xaf, 0x20, 0x00,
|
||||
0x0f, 0x00, 0x33, 0x00, 0x09, 0x08, 0x20, 0x00,
|
||||
0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04, 0x62, 0x00,
|
||||
0x0b, 0x00, 0x01, 0xae, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff};
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
#ifndef SC14421_FIRMWARE
|
||||
#define SC14421_FIRMWARE
|
||||
|
||||
extern const unsigned char sc14421_firmware[509];
|
||||
|
||||
#define DIP_RF_INIT 0x0
|
||||
#define RF_DESC 0x4A
|
||||
#define RX_DESC 0x58
|
||||
#define TX_DESC 0x50
|
||||
#define TRX_DESC_FN 0x6
|
||||
#define SD_RSSI_OFF 0x0
|
||||
#define SD_CSUM_OFF 0x1
|
||||
#define SD_PREAMBLE_OFF 0x1
|
||||
#define SD_DATA_OFF 0x6
|
||||
#define PP0 0x4
|
||||
#define PP2 0x6
|
||||
#define PP4 0x8
|
||||
#define PP6 0xB
|
||||
#define PP8 0xD
|
||||
#define PP10 0xF
|
||||
#define PP12 0x12
|
||||
#define PP14 0x14
|
||||
#define PP16 0x16
|
||||
#define PP18 0x19
|
||||
#define PP20 0x1B
|
||||
#define PP22 0x1D
|
||||
#define JP0 0x3
|
||||
#define JP2 0x5
|
||||
#define JP4 0x7
|
||||
#define JP6 0xA
|
||||
#define JP8 0xC
|
||||
#define JP10 0xE
|
||||
#define JP12 0x11
|
||||
#define JP14 0x13
|
||||
#define JP16 0x15
|
||||
#define JP18 0x18
|
||||
#define JP20 0x1A
|
||||
#define JP22 0x1C
|
||||
#define RFStart 0xCD
|
||||
#define SlotTable 0x2
|
||||
#define SyncInit 0xAE
|
||||
#define Sync 0xAF
|
||||
#define SyncLock 0xBF
|
||||
#define SyncLoop 0xC2
|
||||
#define RecvP32U 0x20
|
||||
#define RecvP32P 0x26
|
||||
#define TransmitP00 0x29
|
||||
#define TransmitP32U 0x2D
|
||||
#define TransmitP32P 0x33
|
||||
|
||||
#endif /* SC14421_FIRMWARE */
|
||||
Reference in New Issue