bnx2x: fix BRB thresholds for dropless_fc mode
Fix the thresholds according to 5778x HW and increase rx_ring size to suit new thresholds in dropless_fc mode. Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Kravkov
David S. Miller
parent
e9278a475f
commit
dfacf1387c
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@ -315,6 +315,14 @@ union db_prod {
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u32 raw;
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};
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/* dropless fc FW/HW related params */
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#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
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#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
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ETH_MAX_AGGREGATION_QUEUES_E1 :\
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ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
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#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
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#define FW_PREFETCH_CNT 16
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#define DROPLESS_FC_HEADROOM 100
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/* MC hsi */
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#define BCM_PAGE_SHIFT 12
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@ -331,15 +339,35 @@ union db_prod {
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/* SGE ring related macros */
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#define NUM_RX_SGE_PAGES 2
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#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
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#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
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#define NEXT_PAGE_SGE_DESC_CNT 2
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#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
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/* RX_SGE_CNT is promised to be a power of 2 */
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#define RX_SGE_MASK (RX_SGE_CNT - 1)
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#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
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#define MAX_RX_SGE (NUM_RX_SGE - 1)
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#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
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(MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
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(MAX_RX_SGE_CNT - 1)) ? \
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(x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
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(x) + 1)
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#define RX_SGE(x) ((x) & MAX_RX_SGE)
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/*
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* Number of required SGEs is the sum of two:
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* 1. Number of possible opened aggregations (next packet for
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* these aggregations will probably consume SGE immidiatelly)
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* 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
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* after placement on BD for new TPA aggregation)
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*
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* Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
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*/
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#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
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(BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
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#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
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MAX_RX_SGE_CNT)
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#define SGE_TH_LO(bp) (NUM_SGE_REQ + \
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NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
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#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
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/* Manipulate a bit vector defined as an array of u64 */
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/* Number of bits in one sge_mask array element */
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@ -551,24 +579,43 @@ struct bnx2x_fastpath {
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#define NUM_TX_RINGS 16
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#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
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#define NEXT_PAGE_TX_DESC_CNT 1
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
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#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
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#define MAX_TX_BD (NUM_TX_BD - 1)
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#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
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#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
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(MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
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(MAX_TX_DESC_CNT - 1)) ? \
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(x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
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(x) + 1)
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#define TX_BD(x) ((x) & MAX_TX_BD)
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#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
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/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
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#define NUM_RX_RINGS 8
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#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
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#define NEXT_PAGE_RX_DESC_CNT 2
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
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#define RX_DESC_MASK (RX_DESC_CNT - 1)
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#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
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#define MAX_RX_BD (NUM_RX_BD - 1)
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#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
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#define MIN_RX_AVAIL 128
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/* dropless fc calculations for BDs
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*
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* Number of BDs should as number of buffers in BRB:
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* Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
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* "next" elements on each page
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*/
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#define NUM_BD_REQ BRB_SIZE(bp)
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#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
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MAX_RX_DESC_CNT)
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#define BD_TH_LO(bp) (NUM_BD_REQ + \
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NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
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FW_DROP_LEVEL(bp))
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#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
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#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
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#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
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ETH_MIN_RX_CQES_WITH_TPA_E1 : \
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@ -579,7 +626,9 @@ struct bnx2x_fastpath {
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MIN_RX_AVAIL))
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#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
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(MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
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(MAX_RX_DESC_CNT - 1)) ? \
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(x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
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(x) + 1)
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#define RX_BD(x) ((x) & MAX_RX_BD)
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/*
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@ -589,14 +638,31 @@ struct bnx2x_fastpath {
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#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
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#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
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#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
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#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
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#define NEXT_PAGE_RCQ_DESC_CNT 1
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#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
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#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
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#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
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#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
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#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
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(MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
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(MAX_RCQ_DESC_CNT - 1)) ? \
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(x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
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(x) + 1)
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#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
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/* dropless fc calculations for RCQs
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*
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* Number of RCQs should be as number of buffers in BRB:
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* Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
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* "next" elements on each page
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*/
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#define NUM_RCQ_REQ BRB_SIZE(bp)
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#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
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MAX_RCQ_DESC_CNT)
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#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
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NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
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FW_DROP_LEVEL(bp))
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#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
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/* This is needed for determining of last_max */
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#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
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@ -987,8 +987,6 @@ void __bnx2x_link_report(struct bnx2x *bp)
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void bnx2x_init_rx_rings(struct bnx2x *bp)
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{
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int func = BP_FUNC(bp);
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int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
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ETH_MAX_AGGREGATION_QUEUES_E1H_E2;
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u16 ring_prod;
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int i, j;
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@ -1001,7 +999,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
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if (!fp->disable_tpa) {
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/* Fill the per-aggregtion pool */
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for (i = 0; i < max_agg_queues; i++) {
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for (i = 0; i < MAX_AGG_QS(bp); i++) {
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struct bnx2x_agg_info *tpa_info =
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&fp->tpa_info[i];
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struct sw_rx_bd *first_buf =
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@ -1041,7 +1039,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
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bnx2x_free_rx_sge_range(bp, fp,
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ring_prod);
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bnx2x_free_tpa_pool(bp, fp,
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max_agg_queues);
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MAX_AGG_QS(bp));
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fp->disable_tpa = 1;
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ring_prod = 0;
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break;
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@ -1137,9 +1135,7 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp)
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bnx2x_free_rx_bds(fp);
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if (!fp->disable_tpa)
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bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
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ETH_MAX_AGGREGATION_QUEUES_E1 :
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ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
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bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
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}
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}
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@ -2756,8 +2756,14 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
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u16 tpa_agg_size = 0;
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if (!fp->disable_tpa) {
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pause->sge_th_hi = 250;
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pause->sge_th_lo = 150;
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pause->sge_th_lo = SGE_TH_LO(bp);
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pause->sge_th_hi = SGE_TH_HI(bp);
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/* validate SGE ring has enough to cross high threshold */
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WARN_ON(bp->dropless_fc &&
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pause->sge_th_hi + FW_PREFETCH_CNT >
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MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
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tpa_agg_size = min_t(u32,
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(min_t(u32, 8, MAX_SKB_FRAGS) *
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SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
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@ -2771,10 +2777,21 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
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/* pause - not for e1 */
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if (!CHIP_IS_E1(bp)) {
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pause->bd_th_hi = 350;
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pause->bd_th_lo = 250;
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pause->rcq_th_hi = 350;
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pause->rcq_th_lo = 250;
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pause->bd_th_lo = BD_TH_LO(bp);
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pause->bd_th_hi = BD_TH_HI(bp);
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pause->rcq_th_lo = RCQ_TH_LO(bp);
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pause->rcq_th_hi = RCQ_TH_HI(bp);
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/*
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* validate that rings have enough entries to cross
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* high thresholds
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*/
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WARN_ON(bp->dropless_fc &&
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pause->bd_th_hi + FW_PREFETCH_CNT >
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bp->rx_ring_size);
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WARN_ON(bp->dropless_fc &&
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pause->rcq_th_hi + FW_PREFETCH_CNT >
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NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
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pause->pri_map = 1;
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}
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@ -2802,9 +2819,7 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
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* For PF Clients it should be the maximum avaliable number.
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* VF driver(s) may want to define it to a smaller value.
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*/
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rxq_init->max_tpa_queues =
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(CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
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ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
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rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
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rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
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rxq_init->fw_sb_id = fp->fw_sb_id;
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