cirrusfb: GD5434 (aka SD64) support fixed
Fix handling of the Cirrus Logic GD5434 chip. Distinguish this chip from the GD5430. It allows detecting memory size for both models correctly. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
parent
8f19e15b8a
commit
df3aafd57d
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@ -145,7 +145,9 @@ static const struct cirrusfb_board_info_rec {
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.scrn_start_bit19 = true,
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.sr07 = 0xF0,
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.sr07_1bpp = 0xF0,
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.sr07_1bpp_mux = 0xF6,
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.sr07_8bpp = 0xF1,
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.sr07_8bpp_mux = 0xF7,
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.sr1f = 0x1E
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},
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[BT_PICCOLO] = {
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@ -262,8 +264,8 @@ static const struct cirrusfb_board_info_rec {
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static struct pci_device_id cirrusfb_pci_table[] = {
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CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
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CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
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CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
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CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
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CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
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CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
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CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
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CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
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@ -341,6 +343,7 @@ struct cirrusfb_info {
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unsigned char SFR; /* Shadow of special function register */
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int multiplexing;
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int doubleVCLK;
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int blank_mode;
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u32 pseudo_palette[16];
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@ -496,18 +499,15 @@ static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
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break;
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}
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}
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#if 0
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/* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
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/* If we have a 1MB 5434, we need to put ourselves in a mode where
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* the VCLK is double the pixel clock. */
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switch (var->bits_per_pixel) {
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case 16:
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case 24:
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if (var->xres <= 800)
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/* Xbh has this type of clock for 32-bit */
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freq /= 2;
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break;
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cinfo->doubleVCLK = 0;
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if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
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var->bits_per_pixel == 16) {
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cinfo->doubleVCLK = 1;
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}
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#endif
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return 0;
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}
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@ -830,10 +830,13 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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vga_wcrt(regbase, CL_CRT1A, tmp);
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freq = PICOS2KHZ(var->pixclock);
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if (cinfo->btype == BT_ALPINE && var->bits_per_pixel == 24)
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freq *= 3;
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if (var->bits_per_pixel == 24)
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if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
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freq *= 3;
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if (cinfo->multiplexing)
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freq /= 2;
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if (cinfo->doubleVCLK)
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freq *= 2;
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bestclock(freq, &nom, &den, &div);
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@ -851,10 +854,9 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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* as clock source
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*/
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int divMCLK = cirrusfb_check_mclk(info, freq);
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if (divMCLK) {
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if (divMCLK)
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nom = 0;
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cirrusfb_set_mclk_as_source(info, divMCLK);
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}
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cirrusfb_set_mclk_as_source(info, divMCLK);
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}
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if (is_laguna(cinfo)) {
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long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
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@ -885,14 +887,13 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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(cinfo->btype == BT_GD5480))
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tmp |= 0x80;
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dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
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/* Laguna chipset has reversed clock registers */
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if (is_laguna(cinfo)) {
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vga_wseq(regbase, CL_SEQRE, tmp);
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vga_wseq(regbase, CL_SEQR1E, nom);
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} else {
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vga_wseq(regbase, CL_SEQRB, nom);
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vga_wseq(regbase, CL_SEQR1B, tmp);
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vga_wseq(regbase, CL_SEQRE, nom);
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vga_wseq(regbase, CL_SEQR1E, tmp);
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}
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}
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@ -911,15 +912,13 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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else
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vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
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/* adjust horizontal/vertical sync type (low/high) */
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/* adjust horizontal/vertical sync type (low/high), use VCLK3 */
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/* enable display memory & CRTC I/O address for color mode */
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tmp = 0x03;
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tmp = 0x03 | 0xc;
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if (var->sync & FB_SYNC_HOR_HIGH_ACT)
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tmp |= 0x40;
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if (var->sync & FB_SYNC_VERT_HIGH_ACT)
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tmp |= 0x80;
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if (is_laguna(cinfo))
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tmp |= 0xc;
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WGen(cinfo, VGA_MIS_W, tmp);
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/* text cursor on and start line */
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@ -1052,9 +1051,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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vga_wseq(regbase, CL_SEQRF, 0xb8);
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#endif
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case BT_ALPINE:
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/* We already set SRF and SR1F */
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break;
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case BT_SD64:
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case BT_GD5480:
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case BT_LAGUNA:
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@ -1103,7 +1099,8 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_PICASSO4:
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case BT_ALPINE:
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/* Extended Sequencer Mode: 256c col. mode */
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vga_wseq(regbase, CL_SEQR7, 0xa7);
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vga_wseq(regbase, CL_SEQR7,
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cinfo->doubleVCLK ? 0xa3 : 0xa7);
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break;
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case BT_GD5480:
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@ -1128,7 +1125,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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/* mode register: 256 color mode */
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vga_wgfx(regbase, VGA_GFX_MODE, 64);
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#ifdef CONFIG_PCI
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WHDR(cinfo, 0xc1); /* Copy Xbh */
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WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
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#elif defined(CONFIG_ZORRO)
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/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
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WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
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@ -1529,7 +1526,9 @@ static void init_vgachip(struct fb_info *info)
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case BT_LAGUNAB:
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break;
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case BT_SD64:
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#ifdef CONFIG_ZORRO
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vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
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#endif
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break;
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default:
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vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
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@ -1604,7 +1603,8 @@ static void init_vgachip(struct fb_info *info)
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/* Bit Mask: no mask at all */
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vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
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if (cinfo->btype == BT_ALPINE || is_laguna(cinfo))
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if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
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is_laguna(cinfo))
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/* (5434 can't have bit 3 set for bitblt) */
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vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
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else
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@ -1809,9 +1809,11 @@ static void cirrusfb_imageblit(struct fb_info *info,
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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/* Alpine acceleration does not work at 24bpp ?!? */
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if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1 ||
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(cinfo->btype == BT_ALPINE && op == 0xc))
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/* Alpine/SD64 does not work at 24bpp ??? */
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if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
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cfb_imageblit(info, image);
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else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
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op == 0xc)
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cfb_imageblit(info, image);
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else {
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unsigned size = ((image->width + 7) >> 3) * image->height;
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@ -1895,7 +1897,7 @@ static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
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/* If DRAM bank switching is enabled, there must be
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* twice as much memory installed. (4MB on the 5434)
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*/
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if (SRF & 0x80)
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if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
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mem *= 2;
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}
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@ -2553,7 +2555,7 @@ static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned ch
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if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
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cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
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is_laguna(cinfo)) {
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cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
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/* but DAC data register IS, at least for Picasso II */
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if (cinfo->btype == BT_PICASSO)
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data += 0xfff;
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