[PATCH] i386: Enable bank 0 on non K7 Athlon
As a bug workaround bank 0 on K7s is normally disabled, but no need to do that on other AMD CPUs. Cc: davej@redhat.com Signed-off-by: Andi Kleen <ak@suse.de>
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1 changed files with 7 additions and 3 deletions
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@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
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nr_mce_banks = l & 0xff;
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/* Clear status for MC index 0 separately, we don't touch CTL,
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* as some Athlons cause spurious MCEs when its enabled. */
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wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
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for (i=1; i<nr_mce_banks; i++) {
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* as some K7 Athlons cause spurious MCEs when its enabled. */
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if (boot_cpu_data.x86 == 6) {
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wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
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i = 1;
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} else
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i = 0;
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for (; i<nr_mce_banks; i++) {
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wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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}
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