[IA64-SGI] - Eliminate SN pio_phys_xxx macros. Move to assembly
Rewrite the SN pio_phys_xxx macros in assembly language. This avoids issues with the Intel icc compiler. Function call overhead is not an issue - the functions reference PIOs and take 100's nsec to complete. In addition, the functions should likely be in assembly language anyway - they reference memory using physical addressing mode. One function executes with psr.ic disabled. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Jack Steiner
Tony Luck
parent
412e6a3782
commit
dcc1dd2366
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@ -10,7 +10,8 @@
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CPPFLAGS += -I$(srctree)/arch/ia64/sn/include
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obj-y += setup.o bte.o bte_error.o irq.o mca.o idle.o \
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huberror.o io_init.o iomv.o klconflib.o sn2/
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huberror.o io_init.o iomv.o klconflib.o pio_phys.o \
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sn2/
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obj-$(CONFIG_IA64_GENERIC) += machvec.o
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obj-$(CONFIG_SGI_TIOCX) += tiocx.o
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obj-$(CONFIG_IA64_SGI_SN_XP) += xp.o
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@ -0,0 +1,71 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
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*
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* This file contains macros used to access MMR registers via
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* uncached physical addresses.
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* pio_phys_read_mmr - read an MMR
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* pio_phys_write_mmr - write an MMR
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* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
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* Second MMR will be skipped if address is NULL
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*
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* Addresses passed to these routines should be uncached physical addresses
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* ie., 0x80000....
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*/
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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GLOBAL_ENTRY(pio_phys_read_mmr)
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.prologue
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.regstk 1,0,0,0
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.body
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mov r2=psr
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rsm psr.i | psr.dt
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;;
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srlz.d
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ld8.acq r8=[r32]
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_phys_read_mmr)
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GLOBAL_ENTRY(pio_phys_write_mmr)
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.prologue
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.regstk 2,0,0,0
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.body
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mov r2=psr
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rsm psr.i | psr.dt
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;;
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srlz.d
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st8.rel [r32]=r33
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_phys_write_mmr)
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GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)
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.prologue
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.regstk 4,0,0,0
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.body
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mov r2=psr
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cmp.ne p9,p0=r34,r0;
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rsm psr.i | psr.dt | psr.ic
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;;
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srlz.d
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st8.rel [r32]=r33
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(p9) st8.rel [r34]=r35
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_atomic_phys_write_mmrs)
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@ -3,15 +3,14 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002-2004 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#ifndef _ASM_IA64_SN_RW_MMR_H
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#define _ASM_IA64_SN_RW_MMR_H
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/*
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* This file contains macros used to access MMR registers via
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* uncached physical addresses.
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* This file that access MMRs via uncached physical addresses.
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* pio_phys_read_mmr - read an MMR
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* pio_phys_write_mmr - write an MMR
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* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
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@ -22,53 +21,8 @@
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*/
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extern inline long
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pio_phys_read_mmr(volatile long *mmr)
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{
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long val;
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"ld8.acq %0=[%1];;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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: "=r"(val)
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: "r"(mmr)
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: "r2");
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return val;
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}
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extern inline void
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pio_phys_write_mmr(volatile long *mmr, long val)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"st8.rel [%0]=%1;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr), "r"(val)
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: "r2", "memory");
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}
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extern inline void
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pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt | psr.ic;;"
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"cmp.ne p9,p0=%2,r0;"
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"srlz.i;;"
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"st8.rel [%0]=%1;"
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"(p9) st8.rel [%2]=%3;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)
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: "p9", "r2", "memory");
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}
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extern long pio_phys_read_mmr(volatile long *mmr);
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extern void pio_phys_write_mmr(volatile long *mmr, long val);
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extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
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#endif /* _ASM_IA64_SN_RW_MMR_H */
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