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A bunch of fixes/updates for the AMD side of EDAC including 

* MCE decoding updates
 * tree-wide EDAC sweep making pci_device_ids __devinitconst
 * Scrub rate API correction
 * two amd64_edac corrections for K8 boxes and sysfs csrow nodes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJPZ0GkAAoJEBLB8Bhh3lVKjr4P/2q+7iZY8skYJqjrGel1vpKG
 aMwn1DTv9Mhy2omE+UDSuMVWrZ8CI/G+5aW5j6uulj6uko+3Q1aQtkN3zQhoa1RG
 7Q2X4t0skRnr7xOJKIYour+ufX4MLoVdEZqu4jvIFoniAQEXbDfbgT7KnA/hRwFp
 i04GaFRsPb97cvi7OfMpczTVan3lDUhT81kvdlrVZGhu3dVIkZw//hmsrt98SF1G
 qeBSvY/ji45D/mro6QMDZcN5+AWgLuI4ivM3Bk1tFgxs6KVaHcCOfPC8szQAuupl
 fQl/N4sHyj7BuTHlCWEog+V67ifpZcb5peya9Vs5nArhj/GzFmVhE0JBgFG7aCXQ
 hnAEhmgUI5NdHhLmrmGWSPOEQbG+V53/mBEk45sdH9zzl7yBH20gILdYFejmwEuX
 HfTTugIby4ncsw9Gkmi2rx33wNuzdOsXNRILk56bSf9X3e1m7LDtZV6EMeQ9I3D9
 ONjrrmNrkz5AmI765IsGs6vJT6ZkpZk6DNbykEOTPtoOhwiCSsbapowh9NpdhL1k
 EwUuZfyWoulVeYJw+m6a6Aw9bp2stj694p0tfdXh4C9g09Qlvx2RANBAgEJQE/oD
 5rWE/p/HiDFuMd7IrRuLaC1vV7YnWNX/EHLvtV7Ei2qslaK9XxFIb9p7jqyUIpoj
 nwUDJYIB4Dbk+NSV34N3
 =Q+wu
 -----END PGP SIGNATURE-----

Merge tag 'amd64-edac-updates-for-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull AMD64 EDAC fixes from Borislav Petkov:
 "A bunch of fixes/updates for the AMD side of EDAC including

   * MCE decoding updates
   * tree-wide EDAC sweep making pci_device_ids __devinitconst
   * Scrub rate API correction
   * two amd64_edac corrections for K8 boxes and sysfs csrow nodes"

* tag 'amd64-edac-updates-for-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  MCE, AMD: Constify error tables
  MCE, AMD: Correct bank 5 error signatures
  MCE, AMD: Rework NB MCE signatures
  MCE, AMD: Correct VB data error description
  MCE, AMD: Correct ucode patch buffer description
  MCE, AMD: Correct some MC0 error types
  EDAC: Make pci_device_id tables __devinitconst.
  EDAC: Correct scrub rate API
  amd64_edac: Fix K8 revD and later chip select sizes
  amd64_edac: Fix missing csrows sysfs nodes
This commit is contained in:
Linus Torvalds 2012-03-23 17:59:47 -07:00
parent cf821923ba ebe2aea868
commit dae430c6f6
22 changed files with 128 additions and 187 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/edac.txt
View File

@ -334,8 +334,8 @@ Sdram memory scrubbing rate:
Reading the file will return the actual scrubbing rate employed.
If configuration fails or memory scrubbing is not implemented, the value
of the attribute file will be -1.
If configuration fails or memory scrubbing is not implemented, accessing
that attribute will fail.

50
drivers/edac/amd64_edac.c
View File

@ -1132,12 +1132,36 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
}
else if (pvt->ext_model >= K8_REV_D) {
unsigned diff;
WARN_ON(cs_mode > 10);
if (cs_mode == 3 || cs_mode == 8)
return 32 << (cs_mode - 1);
else
return 32 << cs_mode;
/*
* the below calculation, besides trying to win an obfuscated C
* contest, maps cs_mode values to DIMM chip select sizes. The
* mappings are:
*
* cs_mode CS size (mb)
* ======= ============
* 0 32
* 1 64
* 2 128
* 3 128
* 4 256
* 5 512
* 6 256
* 7 512
* 8 1024
* 9 1024
* 10 2048
*
* Basically, it calculates a value with which to shift the
* smallest CS size of 32MB.
*
* ddr[23]_cs_size have a similar purpose.
*/
diff = cs_mode/3 + (unsigned)(cs_mode > 5);
return 32 << (cs_mode - diff);
}
else {
WARN_ON(cs_mode > 6);
@ -2133,6 +2157,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
{
u32 cs_mode, nr_pages;
u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
/*
* The math on this doesn't look right on the surface because x/2*4 can
@ -2141,16 +2166,10 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
* number of bits to shift the DBAM register to extract the proper CSROW
* field.
*/
cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;
cs_mode = (dbam >> ((csrow_nr / 2) * 4)) & 0xF;
nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
/*
* If dual channel then double the memory size of single channel.
* Channel count is 1 or 2
*/
nr_pages <<= (pvt->channel_count - 1);
debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
debugf0(" nr_pages= %u channel-count = %d\n",
nr_pages, pvt->channel_count);
@ -2181,7 +2200,7 @@ static int init_csrows(struct mem_ctl_info *mci)
for_each_chip_select(i, 0, pvt) {
csrow = &mci->csrows[i];
if (!csrow_enabled(i, 0, pvt)) {
if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
debugf1("----CSROW %d EMPTY for node %d\n", i,
pvt->mc_node_id);
continue;
@ -2191,7 +2210,10 @@ static int init_csrows(struct mem_ctl_info *mci)
i, pvt->mc_node_id);
empty = 0;
csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
if (csrow_enabled(i, 0, pvt))
csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
if (csrow_enabled(i, 1, pvt))
csrow->nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);
sys_addr = input_addr_to_sys_addr(mci, input_addr_min);
csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
@ -2685,7 +2707,7 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev)
* PCI core identifies what devices are on a system during boot, and then
* inquiry this table to see if this driver is for a given device found.
*/
static const struct pci_device_id amd64_pci_table[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {
{
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,

2
drivers/edac/amd76x_edac.c
View File

@ -321,7 +321,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(amd76x_pci_tbl) = {
{
PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
AMD762},

2
drivers/edac/e752x_edac.c
View File

@ -1380,7 +1380,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(e752x_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
E7520},

2
drivers/edac/e7xxx_edac.c
View File

@ -525,7 +525,7 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
E7205},

4
drivers/edac/edac_mc_sysfs.c
View File

@ -452,7 +452,7 @@ static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
int new_bw = 0;
if (!mci->set_sdram_scrub_rate)
return -EINVAL;
return -ENODEV;
if (strict_strtoul(data, 10, &bandwidth) < 0)
return -EINVAL;
@ -475,7 +475,7 @@ static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
int bandwidth = 0;
if (!mci->get_sdram_scrub_rate)
return -EINVAL;
return -ENODEV;
bandwidth = mci->get_sdram_scrub_rate(mci);
if (bandwidth < 0) {

2
drivers/edac/i3000_edac.c
View File

@ -470,7 +470,7 @@ static void __devexit i3000_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i3000_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i3000_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
I3000},

2
drivers/edac/i3200_edac.c
View File

@ -445,7 +445,7 @@ static void __devexit i3200_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i3200_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
I3200},

2
drivers/edac/i5000_edac.c
View File

@ -1516,7 +1516,7 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev)
*
* The "E500P" device is the first device supported.
*/
static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
.driver_data = I5000P},

2
drivers/edac/i5100_edac.c
View File

@ -1051,7 +1051,7 @@ static void __devexit i5100_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i5100_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
/* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
{ 0, }

2
drivers/edac/i5400_edac.c
View File

@ -1383,7 +1383,7 @@ static void __devexit i5400_remove_one(struct pci_dev *pdev)
*
* The "E500P" device is the first device supported.
*/
static const struct pci_device_id i5400_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i5400_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
{0,} /* 0 terminated list. */
};

2
drivers/edac/i7300_edac.c
View File

@ -1192,7 +1192,7 @@ static void __devexit i7300_remove_one(struct pci_dev *pdev)
*
* Has only 8086:360c PCI ID
*/
static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i7300_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
{0,} /* 0 terminated list. */
};

2
drivers/edac/i7core_edac.c
View File

@ -391,7 +391,7 @@ static const struct pci_id_table pci_dev_table[] = {
/*
* pci_device_id table for which devices we are looking for
*/
static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
{0,} /* 0 terminated list. */

2
drivers/edac/i82443bxgx_edac.c
View File

@ -380,7 +380,7 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},

2
drivers/edac/i82860_edac.c
View File

@ -270,7 +270,7 @@ static void __devexit i82860_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i82860_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
I82860},

2
drivers/edac/i82875p_edac.c
View File

@ -511,7 +511,7 @@ static void __devexit i82875p_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i82875p_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
I82875P},

2
drivers/edac/i82975x_edac.c
View File

@ -612,7 +612,7 @@ static void __devexit i82975x_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id i82975x_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
I82975X

210
drivers/edac/mce_amd.c
View File

@ -39,42 +39,31 @@ EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
*/
/* transaction type */
const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
EXPORT_SYMBOL_GPL(tt_msgs);
/* cache level */
const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
EXPORT_SYMBOL_GPL(ll_msgs);
/* memory transaction type */
const char *rrrr_msgs[] = {
const char * const rrrr_msgs[] = {
"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
};
EXPORT_SYMBOL_GPL(rrrr_msgs);
/* participating processor */
const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
EXPORT_SYMBOL_GPL(pp_msgs);
/* request timeout */
const char *to_msgs[] = { "no timeout", "timed out" };
const char * const to_msgs[] = { "no timeout", "timed out" };
EXPORT_SYMBOL_GPL(to_msgs);
/* memory or i/o */
const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
EXPORT_SYMBOL_GPL(ii_msgs);
static const char *f10h_nb_mce_desc[] = {
"HT link data error",
"Protocol error (link, L3, probe filter, etc.)",
"Parity error in NB-internal arrays",
"Link Retry due to IO link transmission error",
"L3 ECC data cache error",
"ECC error in L3 cache tag",
"L3 LRU parity bits error",
"ECC Error in the Probe Filter directory"
};
static const char * const f15h_ic_mce_desc[] = {
"UC during a demand linefill from L2",
"Parity error during data load from IC",
@ -88,7 +77,7 @@ static const char * const f15h_ic_mce_desc[] = {
"Parity error for IC probe tag valid bit",
"PFB non-cacheable bit parity error",
"PFB valid bit parity error", /* xec = 0xd */
"patch RAM", /* xec = 010 */
"Microcode Patch Buffer", /* xec = 010 */
"uop queue",
"insn buffer",
"predecode buffer",
@ -104,7 +93,7 @@ static const char * const f15h_cu_mce_desc[] = {
"WCC Tag ECC error",
"WCC Data ECC error",
"WCB Data parity error",
"VB Data/ECC error",
"VB Data ECC or parity error",
"L2 Tag ECC error", /* xec = 0x10 */
"Hard L2 Tag ECC error",
"Multiple hits on L2 tag",
@ -112,6 +101,28 @@ static const char * const f15h_cu_mce_desc[] = {
"PRB address parity error"
};
static const char * const nb_mce_desc[] = {
"DRAM ECC error detected on the NB",
"CRC error detected on HT link",
"Link-defined sync error packets detected on HT link",
"HT Master abort",
"HT Target abort",
"Invalid GART PTE entry during GART table walk",
"Unsupported atomic RMW received from an IO link",
"Watchdog timeout due to lack of progress",
"DRAM ECC error detected on the NB",
"SVM DMA Exclusion Vector error",
"HT data error detected on link",
"Protocol error (link, L3, probe filter)",
"NB internal arrays parity error",
"DRAM addr/ctl signals parity error",
"IO link transmission error",
"L3 data cache ECC error", /* xec = 0x1c */
"L3 cache tag error",
"L3 LRU parity bits error",
"ECC Error in the Probe Filter directory"
};
static const char * const fr_ex_mce_desc[] = {
"CPU Watchdog timer expire",
"Wakeup array dest tag",
@ -125,7 +136,7 @@ static const char * const fr_ex_mce_desc[] = {
"Physical register file AG0 port",
"Physical register file AG1 port",
"Flag register file",
"DE correctable error could not be corrected"
"DE error occurred"
};
static bool f12h_dc_mce(u16 ec, u8 xec)
@ -255,10 +266,9 @@ static bool f15h_dc_mce(u16 ec, u8 xec)
} else if (BUS_ERROR(ec)) {
if (!xec)
pr_cont("during system linefill.\n");
pr_cont("System Read Data Error.\n");
else
pr_cont(" Internal %s condition.\n",
((xec == 1) ? "livelock" : "deadlock"));
pr_cont(" Internal error condition type %d.\n", xec);
} else
ret = false;
@ -355,7 +365,11 @@ static bool f15h_ic_mce(u16 ec, u8 xec)
pr_cont("%s.\n", f15h_ic_mce_desc[xec-2]);
break;
case 0x10 ... 0x14:
case 0x10:
pr_cont("%s.\n", f15h_ic_mce_desc[xec-4]);
break;
case 0x11 ... 0x14:
pr_cont("Decoder %s parity error.\n", f15h_ic_mce_desc[xec-4]);
break;
@ -496,58 +510,31 @@ wrong_ls_mce:
pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
}
static bool k8_nb_mce(u16 ec, u8 xec)
void amd_decode_nb_mce(struct mce *m)
{
bool ret = true;
switch (xec) {
case 0x1:
pr_cont("CRC error detected on HT link.\n");
break;
case 0x5:
pr_cont("Invalid GART PTE entry during GART table walk.\n");
break;
case 0x6:
pr_cont("Unsupported atomic RMW received from an IO link.\n");
break;
case 0x0:
case 0x8:
if (boot_cpu_data.x86 == 0x11)
return false;
pr_cont("DRAM ECC error detected on the NB.\n");
break;
case 0xd:
pr_cont("Parity error on the DRAM addr/ctl signals.\n");
break;
default:
ret = false;
break;
}
return ret;
}
static bool f10h_nb_mce(u16 ec, u8 xec)
{
bool ret = true;
struct cpuinfo_x86 *c = &boot_cpu_data;
int node_id = amd_get_nb_id(m->extcpu);
u16 ec = EC(m->status);
u8 xec = XEC(m->status, 0x1f);
u8 offset = 0;
if (k8_nb_mce(ec, xec))
return true;
pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
switch(xec) {
case 0xa ... 0xc:
offset = 10;
break;
switch (xec) {
case 0x0 ... 0xe:
case 0xe:
offset = 11;
/* special handling for DRAM ECCs */
if (xec == 0x0 || xec == 0x8) {
/* no ECCs on F11h */
if (c->x86 == 0x11)
goto wrong_nb_mce;
pr_cont("%s.\n", nb_mce_desc[xec]);
if (nb_bus_decoder)
nb_bus_decoder(node_id, m);
return;
}
break;
case 0xf:
@ -556,83 +543,25 @@ static bool f10h_nb_mce(u16 ec, u8 xec)
else if (BUS_ERROR(ec))
pr_cont("DMA Exclusion Vector Table Walk error.\n");
else
ret = false;
goto out;
break;
goto wrong_nb_mce;
return;
case 0x19:
if (boot_cpu_data.x86 == 0x15)
pr_cont("Compute Unit Data Error.\n");
else
ret = false;
goto out;
break;
goto wrong_nb_mce;
return;
case 0x1c ... 0x1f:
offset = 24;
offset = 13;
break;
default:
ret = false;
goto out;
break;
}
pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
out:
return ret;
}
static bool nb_noop_mce(u16 ec, u8 xec)
{
return false;
}
void amd_decode_nb_mce(struct mce *m)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
int node_id = amd_get_nb_id(m->extcpu);
u16 ec = EC(m->status);
u8 xec = XEC(m->status, 0x1f);
pr_emerg(HW_ERR "Northbridge Error (node %d): ", node_id);
switch (xec) {
case 0x2:
pr_cont("Sync error (sync packets on HT link detected).\n");
return;
case 0x3:
pr_cont("HT Master abort.\n");
return;
case 0x4:
pr_cont("HT Target abort.\n");
return;
case 0x7:
pr_cont("NB Watchdog timeout.\n");
return;
case 0x9:
pr_cont("SVM DMA Exclusion Vector error.\n");
return;
default:
break;
}
if (!fam_ops->nb_mce(ec, xec))
goto wrong_nb_mce;
}
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x15)
if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
nb_bus_decoder(node_id, m);
pr_cont("%s.\n", nb_mce_desc[xec - offset]);
return;
wrong_nb_mce:
@ -648,9 +577,6 @@ static void amd_decode_fr_mce(struct mce *m)
if (c->x86 == 0xf || c->x86 == 0x11)
goto wrong_fr_mce;
if (c->x86 != 0x15 && xec != 0x0)
goto wrong_fr_mce;
pr_emerg(HW_ERR "%s Error: ",
(c->x86 == 0x15 ? "Execution Unit" : "FIROB"));
@ -841,39 +767,33 @@ static int __init mce_amd_init(void)
case 0xf:
fam_ops->dc_mce = k8_dc_mce;
fam_ops->ic_mce = k8_ic_mce;
fam_ops->nb_mce = k8_nb_mce;
break;
case 0x10:
fam_ops->dc_mce = f10h_dc_mce;
fam_ops->ic_mce = k8_ic_mce;
fam_ops->nb_mce = f10h_nb_mce;
break;
case 0x11:
fam_ops->dc_mce = k8_dc_mce;
fam_ops->ic_mce = k8_ic_mce;
fam_ops->nb_mce = f10h_nb_mce;
break;
case 0x12:
fam_ops->dc_mce = f12h_dc_mce;
fam_ops->ic_mce = k8_ic_mce;
fam_ops->nb_mce = nb_noop_mce;
break;
case 0x14:
nb_err_cpumask = 0x3;
fam_ops->dc_mce = f14h_dc_mce;
fam_ops->ic_mce = f14h_ic_mce;
fam_ops->nb_mce = nb_noop_mce;
break;
case 0x15:
xec_mask = 0x1f;
fam_ops->dc_mce = f15h_dc_mce;
fam_ops->ic_mce = f15h_ic_mce;
fam_ops->nb_mce = f10h_nb_mce;
break;
default:

13
drivers/edac/mce_amd.h
View File

@ -69,12 +69,12 @@ enum rrrr_ids {
R4_SNOOP,
};
extern const char *tt_msgs[];
extern const char *ll_msgs[];
extern const char *rrrr_msgs[];
extern const char *pp_msgs[];
extern const char *to_msgs[];
extern const char *ii_msgs[];
extern const char * const tt_msgs[];
extern const char * const ll_msgs[];
extern const char * const rrrr_msgs[];
extern const char * const pp_msgs[];
extern const char * const to_msgs[];
extern const char * const ii_msgs[];
/*
* per-family decoder ops
@ -82,7 +82,6 @@ extern const char *ii_msgs[];
struct amd_decoder_ops {
bool (*dc_mce)(u16, u8);
bool (*ic_mce)(u16, u8);
bool (*nb_mce)(u16, u8);
};
void amd_report_gart_errors(bool);

2
drivers/edac/r82600_edac.c
View File

@ -373,7 +373,7 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(r82600_pci_tbl) = {
{
PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
},

2
drivers/edac/sb_edac.c
View File

@ -367,7 +367,7 @@ static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
/*
* pci_device_id table for which devices we are looking for
*/
static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
{0,} /* 0 terminated list. */
};

2
drivers/edac/x38_edac.c
View File

@ -440,7 +440,7 @@ static void __devexit x38_remove_one(struct pci_dev *pdev)
edac_mc_free(mci);
}
static const struct pci_device_id x38_pci_tbl[] __devinitdata = {
static DEFINE_PCI_DEVICE_TABLE(x38_pci_tbl) = {
{
PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
X38},