OMAP4: hwmod data: Move the DMA structures
The merge of the DMA series on top of the already modified omap_hwmod_data_44xx.c put the dma_system structures at the wrong position in the file. Re-order it properly. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Tested-by: G, Manjunath Kondaiah <manjugk@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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1 changed files with 97 additions and 99 deletions
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@ -254,6 +254,14 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
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};
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};
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/* l3_main_2 interface data */
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/* l3_main_2 interface data */
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/* dma_system -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
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.master = &omap44xx_dma_system_hwmod,
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.slave = &omap44xx_l3_main_2_hwmod,
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.clk = "l3_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* iva -> l3_main_2 */
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/* iva -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
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static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
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.master = &omap44xx_iva_hwmod,
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.master = &omap44xx_iva_hwmod,
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@ -270,14 +278,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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/* dma_system -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
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.master = &omap44xx_dma_system_hwmod,
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.slave = &omap44xx_l3_main_2_hwmod,
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.clk = "l3_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> l3_main_2 */
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/* l4_cfg -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
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.master = &omap44xx_l4_cfg_hwmod,
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.master = &omap44xx_l4_cfg_hwmod,
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@ -506,7 +506,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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* ctrl_module_pad_wkup
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* ctrl_module_pad_wkup
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* ctrl_module_wkup
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* ctrl_module_wkup
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* debugss
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* debugss
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* dma_system
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* dmic
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* dmic
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* dss
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* dss
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* dss_dispc
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* dss_dispc
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@ -576,6 +575,92 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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* usim
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* usim
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*/
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*/
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/*
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* 'dma' class
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* dma controller for data exchange between memory to memory (i.e. internal or
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* external memory) and gp peripherals to memory or memory to gp peripherals
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x002c,
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.syss_offs = 0x0028,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
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.name = "dma",
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.sysc = &omap44xx_dma_sysc,
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};
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/* dma dev_attr */
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static struct omap_dma_dev_attr dma_dev_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
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.lch_count = 32,
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};
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/* dma_system */
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static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
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{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
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{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
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{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
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{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
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};
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/* dma_system master ports */
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static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
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&omap44xx_dma_system__l3_main_2,
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};
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static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
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{
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.pa_start = 0x4a056000,
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.pa_end = 0x4a0560ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> dma_system */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_dma_system_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_dma_system_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dma_system slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
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&omap44xx_l4_cfg__dma_system,
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};
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static struct omap_hwmod omap44xx_dma_system_hwmod = {
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.name = "dma_system",
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.class = &omap44xx_dma_hwmod_class,
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.mpu_irqs = omap44xx_dma_system_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
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.main_clk = "l3_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
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},
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},
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.dev_attr = &dma_dev_attr,
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.slaves = omap44xx_dma_system_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
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.masters = omap44xx_dma_system_masters,
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.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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/*
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* 'dsp' class
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* 'dsp' class
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* dsp sub-system
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* dsp sub-system
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@ -1916,93 +2001,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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};
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/*
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* 'dma' class
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* dma controller for data exchange between memory to memory (i.e. internal or
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* external memory) and gp peripherals to memory or memory to gp peripherals
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x002c,
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.syss_offs = 0x0028,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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/* dma attributes */
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static struct omap_dma_dev_attr dma_dev_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
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.lch_count = 32,
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};
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static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
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.name = "dma",
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.sysc = &omap44xx_dma_sysc,
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};
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/* dma_system */
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static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
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{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
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{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
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{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
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{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
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};
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/* dma_system master ports */
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static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
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&omap44xx_dma_system__l3_main_2,
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};
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static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
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{
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.pa_start = 0x4a056000,
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.pa_end = 0x4a0560ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> dma_system */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_dma_system_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_dma_system_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* dma_system slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
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&omap44xx_l4_cfg__dma_system,
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};
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static struct omap_hwmod omap44xx_dma_system_hwmod = {
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.name = "dma_system",
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.class = &omap44xx_dma_hwmod_class,
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.mpu_irqs = omap44xx_dma_system_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
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.main_clk = "l3_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
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},
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},
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.slaves = omap44xx_dma_system_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
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.masters = omap44xx_dma_system_masters,
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.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
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.dev_attr = &dma_dev_attr,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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/* dmm class */
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/* dmm class */
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&omap44xx_dmm_hwmod,
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&omap44xx_dmm_hwmod,
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@ -2022,12 +2020,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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&omap44xx_l4_per_hwmod,
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&omap44xx_l4_per_hwmod,
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&omap44xx_l4_wkup_hwmod,
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&omap44xx_l4_wkup_hwmod,
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/* dma class */
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&omap44xx_dma_system_hwmod,
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/* mpu_bus class */
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/* mpu_bus class */
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&omap44xx_mpu_private_hwmod,
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&omap44xx_mpu_private_hwmod,
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/* dma class */
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&omap44xx_dma_system_hwmod,
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/* dsp class */
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/* dsp class */
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&omap44xx_dsp_hwmod,
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&omap44xx_dsp_hwmod,
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&omap44xx_dsp_c0_hwmod,
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&omap44xx_dsp_c0_hwmod,
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