spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function
Currently in omap2_mcspi_txrx_dma the tx and the rx support is interleaved. Make the rx related code in omap2_mcspi_rx_dma and the tx related code omap2_mcspi_tx_dma and call the functions. While at it remove the braces in the if statements which has only one line. Also fix ["foo * bar" to "foo *bar"] warn for the rx and tx variables. Only a cleanup no functional change. Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Shubhrajyoti D
Mark Brown
parent
ac2cb30b47
commit
d7b4394e78
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@ -315,6 +315,169 @@ static void omap2_mcspi_tx_callback(void *data)
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omap2_mcspi_set_dma_req(spi, 0, 0);
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}
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static void omap2_mcspi_tx_dma(struct spi_device *spi,
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struct spi_transfer *xfer,
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struct dma_slave_config cfg)
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_dma *mcspi_dma;
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unsigned int count;
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u8 * rx;
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const u8 * tx;
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void __iomem *chstat_reg;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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count = xfer->len;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
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if (mcspi_dma->dma_tx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->tx_dma;
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sg_dma_len(&sg) = xfer->len;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_tx_callback;
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tx->callback_param = spi;
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dmaengine_submit(tx);
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} else {
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/* FIXME: fall back to PIO? */
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}
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}
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dma_async_issue_pending(mcspi_dma->dma_tx);
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omap2_mcspi_set_dma_req(spi, 0, 1);
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wait_for_completion(&mcspi_dma->dma_tx_completion);
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dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
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DMA_TO_DEVICE);
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/* for TX_ONLY mode, be sure all words have shifted out */
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if (rx == NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0)
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dev_err(&spi->dev, "TXS timed out\n");
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else if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_EOT) < 0)
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dev_err(&spi->dev, "EOT timed out\n");
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}
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}
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static unsigned
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omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
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struct dma_slave_config cfg,
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unsigned es)
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_dma *mcspi_dma;
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unsigned int count;
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u32 l;
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int elements = 0;
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int word_len, element_count;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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count = xfer->len;
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word_len = cs->word_len;
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l = mcspi_cached_chconf0(spi);
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if (word_len <= 8)
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element_count = count;
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else if (word_len <= 16)
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element_count = count >> 1;
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else /* word_len <= 32 */
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element_count = count >> 2;
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if (mcspi_dma->dma_rx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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size_t len = xfer->len - es;
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dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
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if (l & OMAP2_MCSPI_CHCONF_TURBO)
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len -= es;
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->rx_dma;
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sg_dma_len(&sg) = len;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
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DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_rx_callback;
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tx->callback_param = spi;
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dmaengine_submit(tx);
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} else {
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/* FIXME: fall back to PIO? */
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}
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}
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dma_async_issue_pending(mcspi_dma->dma_rx);
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omap2_mcspi_set_dma_req(spi, 1, 1);
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
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DMA_FROM_DEVICE);
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omap2_mcspi_set_enable(spi, 0);
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elements = element_count - 1;
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if (l & OMAP2_MCSPI_CHCONF_TURBO) {
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elements--;
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[elements++] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[elements++] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements++] = w;
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} else {
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dev_err(&spi->dev, "DMA RX penultimate word empty");
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count -= (word_len <= 8) ? 2 :
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(word_len <= 16) ? 4 :
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/* word_len <= 32 */ 8;
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omap2_mcspi_set_enable(spi, 1);
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return count;
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}
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}
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[elements] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[elements] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements] = w;
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} else {
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dev_err(&spi->dev, "DMA RX last word empty");
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count -= (word_len <= 8) ? 1 :
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(word_len <= 16) ? 2 :
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/* word_len <= 32 */ 4;
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}
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omap2_mcspi_set_enable(spi, 1);
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return count;
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}
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static unsigned
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omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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{
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@ -322,12 +485,9 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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struct omap2_mcspi_cs *cs = spi->controller_state;
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struct omap2_mcspi_dma *mcspi_dma;
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unsigned int count;
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int word_len, element_count;
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int elements = 0;
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u32 l;
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u8 * rx;
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const u8 * tx;
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void __iomem *chstat_reg;
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u8 *rx;
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const u8 *tx;
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struct dma_slave_config cfg;
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enum dma_slave_buswidth width;
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unsigned es;
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@ -336,7 +496,6 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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l = mcspi_cached_chconf0(spi);
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chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
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if (cs->word_len <= 8) {
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width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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@ -357,144 +516,17 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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cfg.src_maxburst = 1;
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cfg.dst_maxburst = 1;
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if (xfer->tx_buf && mcspi_dma->dma_tx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->tx_dma;
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sg_dma_len(&sg) = xfer->len;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_tx_callback;
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tx->callback_param = spi;
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dmaengine_submit(tx);
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} else {
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/* FIXME: fall back to PIO? */
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}
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}
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if (xfer->rx_buf && mcspi_dma->dma_rx) {
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struct dma_async_tx_descriptor *tx;
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struct scatterlist sg;
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size_t len = xfer->len - es;
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dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
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if (l & OMAP2_MCSPI_CHCONF_TURBO)
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len -= es;
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = xfer->rx_dma;
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sg_dma_len(&sg) = len;
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tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (tx) {
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tx->callback = omap2_mcspi_rx_callback;
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tx->callback_param = spi;
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dmaengine_submit(tx);
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} else {
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/* FIXME: fall back to PIO? */
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}
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}
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count = xfer->len;
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word_len = cs->word_len;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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if (word_len <= 8) {
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element_count = count;
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} else if (word_len <= 16) {
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element_count = count >> 1;
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} else /* word_len <= 32 */ {
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element_count = count >> 2;
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}
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count = xfer->len;
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if (tx != NULL) {
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dma_async_issue_pending(mcspi_dma->dma_tx);
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omap2_mcspi_set_dma_req(spi, 0, 1);
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}
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if (tx != NULL)
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omap2_mcspi_tx_dma(spi, xfer, cfg);
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if (rx != NULL) {
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dma_async_issue_pending(mcspi_dma->dma_rx);
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omap2_mcspi_set_dma_req(spi, 1, 1);
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}
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if (rx != NULL)
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return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
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if (tx != NULL) {
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wait_for_completion(&mcspi_dma->dma_tx_completion);
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dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
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DMA_TO_DEVICE);
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/* for TX_ONLY mode, be sure all words have shifted out */
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if (rx == NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0)
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dev_err(&spi->dev, "TXS timed out\n");
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else if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_EOT) < 0)
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dev_err(&spi->dev, "EOT timed out\n");
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}
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}
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if (rx != NULL) {
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
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DMA_FROM_DEVICE);
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omap2_mcspi_set_enable(spi, 0);
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elements = element_count - 1;
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if (l & OMAP2_MCSPI_CHCONF_TURBO) {
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elements--;
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[elements++] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[elements++] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements++] = w;
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} else {
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dev_err(&spi->dev,
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"DMA RX penultimate word empty");
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count -= (word_len <= 8) ? 2 :
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(word_len <= 16) ? 4 :
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/* word_len <= 32 */ 8;
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omap2_mcspi_set_enable(spi, 1);
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return count;
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}
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}
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if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
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& OMAP2_MCSPI_CHSTAT_RXS)) {
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u32 w;
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w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
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if (word_len <= 8)
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((u8 *)xfer->rx_buf)[elements] = w;
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else if (word_len <= 16)
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((u16 *)xfer->rx_buf)[elements] = w;
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else /* word_len <= 32 */
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((u32 *)xfer->rx_buf)[elements] = w;
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} else {
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dev_err(&spi->dev, "DMA RX last word empty");
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count -= (word_len <= 8) ? 1 :
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(word_len <= 16) ? 2 :
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/* word_len <= 32 */ 4;
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}
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omap2_mcspi_set_enable(spi, 1);
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}
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return count;
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}
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