[ARM] 5195/1: ARMv7 Oprofile support
Add Oprofile kernel support for ARMv7. Tested on OMAP3430 and OMAP3530 chipsets (Cortex-A8). Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Jean PIHET
Russell King
parent
46097c7dd8
commit
d7ac4e28cc
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@ -178,6 +178,11 @@ config OPROFILE_MPCORE
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config OPROFILE_ARM11_CORE
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bool
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config OPROFILE_ARMV7
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def_bool y
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depends on CPU_V7 && !SMP
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bool
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endif
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config VECTORS_BASE
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@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o
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oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o
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oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o
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oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o
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oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o
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@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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spec = &op_mpcore_spec;
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#endif
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#ifdef CONFIG_OPROFILE_ARMV7
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spec = &op_armv7_spec;
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#endif
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if (spec) {
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ret = spec->init();
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if (ret < 0)
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@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec;
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extern struct op_arm_model_spec op_armv6_spec;
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extern struct op_arm_model_spec op_mpcore_spec;
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extern struct op_arm_model_spec op_armv7_spec;
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extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth);
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@ -0,0 +1,411 @@
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/**
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* op_model_v7.c
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* ARM V7 (Cortex A8) Event Monitor Driver
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*
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* Copyright 2008 Jean Pihet <jpihet@mvista.com>
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* Copyright 2004 ARM SMP Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include "op_counter.h"
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#include "op_arm_model.h"
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#include "op_model_v7.h"
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/* #define DEBUG */
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/*
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* ARM V7 PMNC support
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*/
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static u32 cnt_en[CNTMAX];
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static inline void armv7_pmnc_write(u32 val)
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{
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val &= PMNC_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
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}
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static inline u32 armv7_pmnc_read(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
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return val;
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}
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static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = CNTENS_C;
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else
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val = (1 << (cnt - CNT0));
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val &= CNTENS_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = CNTENC_C;
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else
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val = (1 << (cnt - CNT0));
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val &= CNTENC_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_enable_intens(unsigned int cnt)
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{
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u32 val;
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if (cnt >= CNTMAX) {
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printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
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" interrupt enable %d\n", smp_processor_id(), cnt);
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return -1;
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}
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if (cnt == CCNT)
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val = INTENS_C;
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else
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val = (1 << (cnt - CNT0));
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val &= INTENS_MASK;
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asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
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return cnt;
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}
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static inline u32 armv7_pmnc_getreset_flags(void)
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{
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u32 val;
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/* Read */
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asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
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/* Write to clear flags */
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val &= FLAG_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
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return val;
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}
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static inline int armv7_pmnc_select_counter(unsigned int cnt)
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{
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u32 val;
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if ((cnt == CCNT) || (cnt >= CNTMAX)) {
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printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri"
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" %d\n", smp_processor_id(), cnt);
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return -1;
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}
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val = (cnt - CNT0) & SELECT_MASK;
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asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
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return cnt;
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}
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static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
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{
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if (armv7_pmnc_select_counter(cnt) == cnt) {
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val &= EVTSEL_MASK;
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asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
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}
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}
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static void armv7_pmnc_reset_counter(unsigned int cnt)
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{
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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u32 val = -(u32)counter_config[cpu_cnt].count;
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switch (cnt) {
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case CCNT:
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armv7_pmnc_disable_counter(cnt);
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asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
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if (cnt_en[cnt] != 0)
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armv7_pmnc_enable_counter(cnt);
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break;
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case CNT0:
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case CNT1:
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case CNT2:
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case CNT3:
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armv7_pmnc_disable_counter(cnt);
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if (armv7_pmnc_select_counter(cnt) == cnt)
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asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
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if (cnt_en[cnt] != 0)
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armv7_pmnc_enable_counter(cnt);
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break;
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default:
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printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter"
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" %d\n", smp_processor_id(), cnt);
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break;
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}
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}
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int armv7_setup_pmnc(void)
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{
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unsigned int cnt;
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if (armv7_pmnc_read() & PMNC_E) {
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printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup"
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" new event counter.\n", smp_processor_id());
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return -EBUSY;
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}
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/*
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* Initialize & Reset PMNC: C bit, D bit and P bit.
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* Note: Using a slower count for CCNT (D bit: divide by 64) results
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* in a more stable system
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*/
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armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D);
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for (cnt = CCNT; cnt < CNTMAX; cnt++) {
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unsigned long event;
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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/*
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* Disable counter
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*/
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armv7_pmnc_disable_counter(cnt);
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cnt_en[cnt] = 0;
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if (!counter_config[cpu_cnt].enabled)
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continue;
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event = counter_config[cpu_cnt].event & 255;
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/*
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* Set event (if destined for PMNx counters)
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* We don't need to set the event if it's a cycle count
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*/
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if (cnt != CCNT)
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armv7_pmnc_write_evtsel(cnt, event);
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/*
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* Enable interrupt for this counter
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*/
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armv7_pmnc_enable_intens(cnt);
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/*
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* Reset counter
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*/
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armv7_pmnc_reset_counter(cnt);
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/*
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* Enable counter
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*/
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armv7_pmnc_enable_counter(cnt);
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cnt_en[cnt] = 1;
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}
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return 0;
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}
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static inline void armv7_start_pmnc(void)
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{
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armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
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}
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static inline void armv7_stop_pmnc(void)
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{
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armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
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}
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/*
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* CPU counters' IRQ handler (one IRQ per CPU)
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*/
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static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
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{
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struct pt_regs *regs = get_irq_regs();
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unsigned int cnt;
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u32 flags;
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/*
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* Stop IRQ generation
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*/
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armv7_stop_pmnc();
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/*
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* Get and reset overflow status flags
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*/
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flags = armv7_pmnc_getreset_flags();
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/*
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* Cycle counter
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*/
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if (flags & FLAG_C) {
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT);
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armv7_pmnc_reset_counter(CCNT);
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oprofile_add_sample(regs, cpu_cnt);
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}
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/*
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* PMNC counters 0:3
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*/
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for (cnt = CNT0; cnt < CNTMAX; cnt++) {
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if (flags & (1 << (cnt - CNT0))) {
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u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
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armv7_pmnc_reset_counter(cnt);
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oprofile_add_sample(regs, cpu_cnt);
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}
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}
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/*
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* Allow IRQ generation
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*/
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armv7_start_pmnc();
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return IRQ_HANDLED;
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}
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int armv7_request_interrupts(int *irqs, int nr)
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{
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unsigned int i;
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int ret = 0;
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for (i = 0; i < nr; i++) {
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ret = request_irq(irqs[i], armv7_pmnc_interrupt,
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IRQF_DISABLED, "CP15 PMNC", NULL);
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if (ret != 0) {
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printk(KERN_ERR "oprofile: unable to request IRQ%u"
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" for ARMv7\n",
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irqs[i]);
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break;
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}
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}
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if (i != nr)
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while (i-- != 0)
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free_irq(irqs[i], NULL);
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return ret;
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}
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void armv7_release_interrupts(int *irqs, int nr)
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{
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unsigned int i;
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for (i = 0; i < nr; i++)
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free_irq(irqs[i], NULL);
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}
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#ifdef DEBUG
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static void armv7_pmnc_dump_regs(void)
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{
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u32 val;
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unsigned int cnt;
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printk(KERN_INFO "PMNC registers dump:\n");
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asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
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printk(KERN_INFO "PMNC =0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
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printk(KERN_INFO "CNTENS=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
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printk(KERN_INFO "INTENS=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
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printk(KERN_INFO "FLAGS =0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
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printk(KERN_INFO "SELECT=0x%08x\n", val);
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asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
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printk(KERN_INFO "CCNT =0x%08x\n", val);
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for (cnt = CNT0; cnt < CNTMAX; cnt++) {
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armv7_pmnc_select_counter(cnt);
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asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
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printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val);
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asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
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printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val);
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}
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}
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#endif
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static int irqs[] = {
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#ifdef CONFIG_ARCH_OMAP3
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INT_34XX_BENCH_MPU_EMUL,
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#endif
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};
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static void armv7_pmnc_stop(void)
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{
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#ifdef DEBUG
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armv7_pmnc_dump_regs();
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#endif
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armv7_stop_pmnc();
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armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
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}
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static int armv7_pmnc_start(void)
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{
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int ret;
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#ifdef DEBUG
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armv7_pmnc_dump_regs();
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#endif
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ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
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if (ret >= 0)
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armv7_start_pmnc();
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return ret;
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}
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static int armv7_detect_pmnc(void)
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{
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return 0;
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}
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struct op_arm_model_spec op_armv7_spec = {
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.init = armv7_detect_pmnc,
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.num_counters = 5,
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.setup_ctrs = armv7_setup_pmnc,
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.start = armv7_pmnc_start,
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.stop = armv7_pmnc_stop,
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.name = "arm/armv7",
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};
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@ -0,0 +1,103 @@
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/**
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* op_model_v7.h
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* ARM v7 (Cortex A8) Event Monitor Driver
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*
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* Copyright 2008 Jean Pihet <jpihet@mvista.com>
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* Copyright 2004 ARM SMP Development Team
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* Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
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* Copyright 2000-2004 MontaVista Software Inc
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* Copyright 2004 Dave Jiang <dave.jiang@intel.com>
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* Copyright 2004 Intel Corporation
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* Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
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* Copyright 2004 Oprofile Authors
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*
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* Read the file COPYING
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OP_MODEL_V7_H
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#define OP_MODEL_V7_H
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/*
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* Per-CPU PMNC: config reg
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*/
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#define PMNC_E (1 << 0) /* Enable all counters */
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#define PMNC_P (1 << 1) /* Reset all counters */
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#define PMNC_C (1 << 2) /* Cycle counter reset */
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#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define PMNC_X (1 << 4) /* Export to ETM */
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#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define PMNC_MASK 0x3f /* Mask for writable bits */
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/*
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* Available counters
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*/
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#define CCNT 0
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#define CNT0 1
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#define CNT1 2
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#define CNT2 3
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#define CNT3 4
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#define CNTMAX 5
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|
||||
#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter))
|
||||
|
||||
/*
|
||||
* CNTENS: counters enable reg
|
||||
*/
|
||||
#define CNTENS_P0 (1 << 0)
|
||||
#define CNTENS_P1 (1 << 1)
|
||||
#define CNTENS_P2 (1 << 2)
|
||||
#define CNTENS_P3 (1 << 3)
|
||||
#define CNTENS_C (1 << 31)
|
||||
#define CNTENS_MASK 0x8000000f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* CNTENC: counters disable reg
|
||||
*/
|
||||
#define CNTENC_P0 (1 << 0)
|
||||
#define CNTENC_P1 (1 << 1)
|
||||
#define CNTENC_P2 (1 << 2)
|
||||
#define CNTENC_P3 (1 << 3)
|
||||
#define CNTENC_C (1 << 31)
|
||||
#define CNTENC_MASK 0x8000000f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* INTENS: counters overflow interrupt enable reg
|
||||
*/
|
||||
#define INTENS_P0 (1 << 0)
|
||||
#define INTENS_P1 (1 << 1)
|
||||
#define INTENS_P2 (1 << 2)
|
||||
#define INTENS_P3 (1 << 3)
|
||||
#define INTENS_C (1 << 31)
|
||||
#define INTENS_MASK 0x8000000f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* EVTSEL: Event selection reg
|
||||
*/
|
||||
#define EVTSEL_MASK 0x7f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* SELECT: Counter selection reg
|
||||
*/
|
||||
#define SELECT_MASK 0x1f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* FLAG: counters overflow flag status reg
|
||||
*/
|
||||
#define FLAG_P0 (1 << 0)
|
||||
#define FLAG_P1 (1 << 1)
|
||||
#define FLAG_P2 (1 << 2)
|
||||
#define FLAG_P3 (1 << 3)
|
||||
#define FLAG_C (1 << 31)
|
||||
#define FLAG_MASK 0x8000000f /* Mask for writable bits */
|
||||
|
||||
|
||||
int armv7_setup_pmu(void);
|
||||
int armv7_start_pmu(void);
|
||||
int armv7_stop_pmu(void);
|
||||
int armv7_request_interrupts(int *, int);
|
||||
void armv7_release_interrupts(int *, int);
|
||||
|
||||
#endif
|
||||
|
|
@ -280,6 +280,8 @@
|
|||
#define INT_24XX_USB_IRQ_OTG 80
|
||||
#define INT_24XX_MMC_IRQ 83
|
||||
|
||||
#define INT_34XX_BENCH_MPU_EMUL 3
|
||||
|
||||
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
|
||||
* 16 MPUIO lines */
|
||||
#define OMAP_MAX_GPIO_LINES 192
|
||||
|
|
|
|||
Reference in New Issue