spi/pxa2xx: Add CE4100 support
Sodaville's SPI controller is very much the same as in PXA25x. The difference: - The RX/TX FIFO is only 4 words deep instead of 16 - No DMA support - The SPI controller offers a CS functionality Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
This commit is contained in:
Sebastian Andrzej Siewior
parent
8348c259dd
commit
d6ea3df0d4
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@ -267,12 +267,15 @@ config SPI_PPC4xx
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config SPI_PXA2XX
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tristate "PXA2xx SSP SPI master"
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depends on ARCH_PXA && EXPERIMENTAL
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select PXA_SSP
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depends on (ARCH_PXA || (X86_32 && PCI)) && EXPERIMENTAL
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select PXA_SSP if ARCH_PXA
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help
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This enables using a PXA2xx SSP port as a SPI master controller.
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The driver can be configured to use any SSP port and additional
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documentation can be found a Documentation/spi/pxa2xx.
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This enables using a PXA2xx or Sodaville SSP port as a SPI master
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controller. The driver can be configured to use any SSP port and
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additional documentation can be found a Documentation/spi/pxa2xx.
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config SPI_PXA2XX_PCI
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def_bool SPI_PXA2XX && X86_32 && PCI
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config SPI_S3C24XX
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tristate "Samsung S3C24XX series SPI"
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@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += pxa2xx_spi_pci.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
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obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
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obj-$(CONFIG_SPI_OMAP_100K) += omap_spi_100k.o
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@ -28,7 +28,6 @@
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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@ -0,0 +1,201 @@
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/*
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* CE4100's SPI device is more or less the same one as found on PXA
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*
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*/
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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struct awesome_struct {
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struct ssp_device ssp;
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struct platform_device spi_pdev;
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struct pxa2xx_spi_master spi_pdata;
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};
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static DEFINE_MUTEX(ssp_lock);
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static LIST_HEAD(ssp_list);
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struct ssp_device *pxa_ssp_request(int port, const char *label)
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{
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struct ssp_device *ssp = NULL;
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mutex_lock(&ssp_lock);
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list_for_each_entry(ssp, &ssp_list, node) {
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if (ssp->port_id == port && ssp->use_count == 0) {
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ssp->use_count++;
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ssp->label = label;
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break;
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}
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}
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mutex_unlock(&ssp_lock);
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if (&ssp->node == &ssp_list)
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return NULL;
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return ssp;
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}
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EXPORT_SYMBOL_GPL(pxa_ssp_request);
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void pxa_ssp_free(struct ssp_device *ssp)
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{
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mutex_lock(&ssp_lock);
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if (ssp->use_count) {
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ssp->use_count--;
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ssp->label = NULL;
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} else
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dev_err(&ssp->pdev->dev, "device already free\n");
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mutex_unlock(&ssp_lock);
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}
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EXPORT_SYMBOL_GPL(pxa_ssp_free);
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static void plat_dev_release(struct device *dev)
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{
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struct awesome_struct *as = container_of(dev,
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struct awesome_struct, spi_pdev.dev);
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of_device_node_put(&as->spi_pdev.dev);
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}
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static int __devinit ce4100_spi_probe(struct pci_dev *dev,
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const struct pci_device_id *ent)
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{
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int ret;
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resource_size_t phys_beg;
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resource_size_t phys_len;
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struct awesome_struct *spi_info;
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struct platform_device *pdev;
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struct pxa2xx_spi_master *spi_pdata;
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struct ssp_device *ssp;
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ret = pci_enable_device(dev);
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if (ret)
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return ret;
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phys_beg = pci_resource_start(dev, 0);
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phys_len = pci_resource_len(dev, 0);
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if (!request_mem_region(phys_beg, phys_len,
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"CE4100 SPI")) {
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dev_err(&dev->dev, "Can't request register space.\n");
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ret = -EBUSY;
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return ret;
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}
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spi_info = kzalloc(sizeof(*spi_info), GFP_KERNEL);
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if (!spi_info) {
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ret = -ENOMEM;
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goto err_kz;
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}
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ssp = &spi_info->ssp;
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pdev = &spi_info->spi_pdev;
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spi_pdata = &spi_info->spi_pdata;
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pdev->name = "pxa2xx-spi";
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pdev->id = dev->devfn;
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pdev->dev.parent = &dev->dev;
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pdev->dev.platform_data = &spi_info->spi_pdata;
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#ifdef CONFIG_OF
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pdev->dev.of_node = dev->dev.of_node;
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#endif
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pdev->dev.release = plat_dev_release;
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spi_pdata->num_chipselect = dev->devfn;
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ssp->phys_base = pci_resource_start(dev, 0);
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ssp->mmio_base = ioremap(phys_beg, phys_len);
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if (!ssp->mmio_base) {
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dev_err(&pdev->dev, "failed to ioremap() registers\n");
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ret = -EIO;
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goto err_remap;
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}
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ssp->irq = dev->irq;
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ssp->port_id = pdev->id;
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ssp->type = PXA25x_SSP;
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mutex_lock(&ssp_lock);
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list_add(&ssp->node, &ssp_list);
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mutex_unlock(&ssp_lock);
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pci_set_drvdata(dev, spi_info);
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ret = platform_device_register(pdev);
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if (ret)
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goto err_dev_add;
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return ret;
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err_dev_add:
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pci_set_drvdata(dev, NULL);
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mutex_lock(&ssp_lock);
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list_del(&ssp->node);
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mutex_unlock(&ssp_lock);
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iounmap(ssp->mmio_base);
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err_remap:
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kfree(spi_info);
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err_kz:
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release_mem_region(phys_beg, phys_len);
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return ret;
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}
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static void __devexit ce4100_spi_remove(struct pci_dev *dev)
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{
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struct awesome_struct *spi_info;
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struct platform_device *pdev;
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struct ssp_device *ssp;
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spi_info = pci_get_drvdata(dev);
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ssp = &spi_info->ssp;
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pdev = &spi_info->spi_pdev;
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platform_device_unregister(pdev);
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iounmap(ssp->mmio_base);
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release_mem_region(pci_resource_start(dev, 0),
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pci_resource_len(dev, 0));
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mutex_lock(&ssp_lock);
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list_del(&ssp->node);
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mutex_unlock(&ssp_lock);
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pci_set_drvdata(dev, NULL);
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pci_disable_device(dev);
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kfree(spi_info);
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}
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static struct pci_device_id ce4100_spi_devices[] __devinitdata = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e6a) },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, ce4100_spi_devices);
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static struct pci_driver ce4100_spi_driver = {
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.name = "ce4100_spi",
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.id_table = ce4100_spi_devices,
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.probe = ce4100_spi_probe,
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.remove = __devexit_p(ce4100_spi_remove),
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};
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static int __init ce4100_spi_init(void)
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{
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return pci_register_driver(&ce4100_spi_driver);
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}
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module_init(ce4100_spi_init);
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static void __exit ce4100_spi_exit(void)
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{
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pci_unregister_driver(&ce4100_spi_driver);
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}
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module_exit(ce4100_spi_exit);
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MODULE_DESCRIPTION("CE4100 PCI-SPI glue code for PXA's driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
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@ -19,7 +19,6 @@
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#define __linux_pxa2xx_spi_h
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#include <linux/pxa2xx_ssp.h>
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#include <mach/dma.h>
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#define PXA2XX_CS_ASSERT (0x01)
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#define PXA2XX_CS_DEASSERT (0x02)
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@ -44,6 +43,110 @@ struct pxa2xx_spi_chip {
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_ARCH_PXA
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#include <linux/clk.h>
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#include <mach/dma.h>
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extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
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#else
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/*
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* This is the implemtation for CE4100 on x86. ARM defines them in mach/ or
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* plat/ include path.
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* The CE4100 does not provide DMA support. This bits are here to let the driver
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* compile and will never be used. Maybe we get DMA support at a later point in
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* time.
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*/
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#define DCSR(n) (n)
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#define DSADR(n) (n)
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#define DTADR(n) (n)
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#define DCMD(n) (n)
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#define DRCMR(n) (n)
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#define DCSR_RUN (1 << 31) /* Run Bit */
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#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */
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#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */
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#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
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#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
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#define DCSR_ENDINTR (1 << 2) /* End Interrupt */
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#define DCSR_STARTINTR (1 << 1) /* Start Interrupt */
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#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */
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#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */
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#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
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#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
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#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
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#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
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#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR (1 << 9) /* The end of Receive */
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#define DRCMR_MAPVLD (1 << 7) /* Map Valid */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number */
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#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */
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#define DDADR_STOP (1 << 0) /* Stop */
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#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
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#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
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#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
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#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
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#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
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#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
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#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
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#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
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#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
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#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
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#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
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#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
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#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
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#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/*
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* Descriptor structure for PXA's DMA engine
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* Note: this structure must always be aligned to a 16-byte boundary.
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*/
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 1,
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DMA_PRIO_LOW = 2
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} pxa_dma_prio;
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/*
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* DMA registration
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*/
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static inline int pxa_request_dma(char *name,
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pxa_dma_prio prio,
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void (*irq_handler)(int, void *),
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void *data)
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{
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return -ENODEV;
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}
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static inline void pxa_free_dma(int dma_ch)
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{
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}
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/*
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* The CE4100 does not have the clk framework implemented and SPI clock can
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* not be switched on/off or the divider changed.
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*/
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static inline void clk_disable(struct clk *clk)
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{
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}
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static inline int clk_enable(struct clk *clk)
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{
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return 0;
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}
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static inline unsigned long clk_get_rate(struct clk *clk)
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{
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return 3686400;
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}
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#endif
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#endif
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