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ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig

Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with
L1 cache lines which are 64bytes to indicate this without having to
alter the arch/arm/mm/Kconfig entry each time.

Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value
uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6.

Acked-by: Ben Dooks <ben-linux@fluff.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Kukjin Kim 2010-02-22 00:02:59 +01:00 committed by Russell King
parent 3b43816f68
commit d6d502fa4b
3 changed files with 8 additions and 1 deletions

View File

@ -165,6 +165,11 @@ config ARCH_MTD_XIP
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config ARM_L1_CACHE_SHIFT_6
bool
help
Setting ARM L1 cache line size to 64 Bytes.
if OPROFILE
config OPROFILE_ARMV6
@ -642,6 +647,7 @@ config ARCH_S5PC1XX
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
help
Samsung S5PC1XX series based systems

View File

@ -779,5 +779,5 @@ config CACHE_XSC3L2
config ARM_L1_CACHE_SHIFT
int
default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
default 6 if ARM_L1_CACHE_SHIFT_6
default 5

View File

@ -22,6 +22,7 @@ config ARCH_OMAP3
bool "TI OMAP3"
select CPU_V7
select COMMON_CLKDEV
select ARM_L1_CACHE_SHIFT_6
config ARCH_OMAP4
bool "TI OMAP4"