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x86, Calgary: Limit the max PHB number to 256 

The x3950 family can have as many as 256 PCI buses in a single system, so
change the limits to the maximum.  Since there can only be 256 PCI buses in one
domain, we no longer need the BUG_ON check.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Darrick J. Wong 2010-06-30 17:45:19 -07:00 committed by H. Peter Anvin
parent 980019d74e
commit d596043d71
1 changed files with 1 additions and 3 deletions
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4
arch/x86/kernel/pci-calgary_64.c
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@ -110,7 +110,7 @@ int use_calgary __read_mostly = 0;
* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
*/
#define MAX_PHB_BUS_NUM 384
#define MAX_PHB_BUS_NUM 256
#define PHBS_PER_CALGARY 4
@ -1056,8 +1056,6 @@ static int __init calgary_init_one(struct pci_dev *dev)
struct iommu_table *tbl;
int ret;
BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
bbar = busno_to_bbar(dev->bus->number);
ret = calgary_setup_tar(dev, bbar);
if (ret)