davinci: update DM644x support in preparation for more SoCs
Rework DM644x code into SoC specific and board specific parts. This is also to generalize the structure a bit so it's easier to add support for new SoCs in the DaVinci family. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Kevin Hilman
parent
73d3c68f09
commit
d0e47fba05
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@ -4,19 +4,18 @@ menu "TI DaVinci Implementations"
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comment "DaVinci Core Type"
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config ARCH_DAVINCI644x
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default y
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config ARCH_DAVINCI_DM644x
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bool "DaVinci 644x based system"
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comment "DaVinci Board Type"
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config MACH_DAVINCI_EVM
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bool "TI DaVinci EVM"
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bool "TI DM644x EVM"
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default y
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depends on ARCH_DAVINCI644x
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depends on ARCH_DAVINCI_DM644x
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help
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Configure this option to specify the whether the board used
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for development is a DaVinci EVM
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for development is a DM644x EVM
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config DAVINCI_MUX
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@ -9,5 +9,8 @@ obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
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obj-$(CONFIG_DAVINCI_MUX) += mux.o
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# Chip specific
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obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
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# Board specific
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
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@ -15,15 +15,19 @@
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/leds.h>
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#include <linux/memory.h>
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#include <linux/i2c.h>
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#include <linux/i2c/pcf857x.h>
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#include <linux/i2c/at24.h>
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#include <linux/etherdevice.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/io.h>
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#include <linux/phy.h>
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#include <linux/clk.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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@ -32,28 +36,34 @@
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#include <asm/mach/map.h>
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#include <asm/mach/flash.h>
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#include <mach/hardware.h>
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#include <mach/dm644x.h>
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#include <mach/common.h>
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#include <mach/i2c.h>
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#include <mach/serial.h>
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#include <mach/mux.h>
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#include <mach/psc.h>
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#include <mach/nand.h>
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#define DM644X_EVM_PHY_MASK (0x2)
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#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
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#define DAVINCI_CFC_ATA_BASE 0x01C66000
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#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
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/* other misc. init functions */
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void __init davinci_psc_init(void);
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void __init davinci_irq_init(void);
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void __init davinci_map_common_io(void);
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void __init davinci_init_common_hw(void);
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#if defined(CONFIG_MTD_PHYSMAP) || \
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defined(CONFIG_MTD_PHYSMAP_MODULE)
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#define LXT971_PHY_ID (0x001378e2)
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#define LXT971_PHY_MASK (0xfffffff0)
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static struct mtd_partition davinci_evm_norflash_partitions[] = {
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/* bootloader (U-Boot, etc) in first 4 sectors */
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/* bootloader (UBL, U-Boot, etc) in first 5 sectors */
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{
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.name = "bootloader",
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.offset = 0,
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.size = 4 * SZ_64K,
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.size = 5 * SZ_64K,
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.mask_flags = MTD_WRITEABLE, /* force read-only */
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},
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/* bootloader params in the next 1 sectors */
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@ -103,10 +113,60 @@ static struct platform_device davinci_evm_norflash_device = {
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.resource = &davinci_evm_norflash_resource,
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};
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#endif
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struct mtd_partition davinci_evm_nandflash_partition[] = {
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/* 5 MB space at the beginning for bootloader and kernel */
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{
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.name = "NAND filesystem",
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.offset = 5 * SZ_1M,
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.size = MTDPART_SIZ_FULL,
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.mask_flags = 0,
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}
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};
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#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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static struct davinci_nand_pdata davinci_evm_nandflash_data = {
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.parts = davinci_evm_nandflash_partition,
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.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
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.ecc_mode = NAND_ECC_HW,
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};
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static struct resource davinci_evm_nandflash_resource[] = {
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{
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.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device davinci_evm_nandflash_device = {
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.name = "davinci_nand",
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.id = 0,
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.dev = {
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.platform_data = &davinci_evm_nandflash_data,
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},
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.num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
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.resource = davinci_evm_nandflash_resource,
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};
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static u64 davinci_fb_dma_mask = DMA_32BIT_MASK;
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static struct platform_device davinci_fb_device = {
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.name = "davincifb",
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.id = -1,
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.dev = {
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.dma_mask = &davinci_fb_dma_mask,
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.coherent_dma_mask = DMA_32BIT_MASK,
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},
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.num_resources = 0,
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};
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static struct platform_device rtc_dev = {
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.name = "rtc_davinci_evm",
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.id = -1,
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};
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static struct resource ide_resources[] = {
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{
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@ -121,7 +181,7 @@ static struct resource ide_resources[] = {
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},
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};
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static u64 ide_dma_mask = DMA_BIT_MASK(32);
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static u64 ide_dma_mask = DMA_32BIT_MASK;
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static struct platform_device ide_dev = {
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.name = "palm_bk3710",
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@ -130,12 +190,10 @@ static struct platform_device ide_dev = {
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.num_resources = ARRAY_SIZE(ide_resources),
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.dev = {
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.dma_mask = &ide_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.coherent_dma_mask = DMA_32BIT_MASK,
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},
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};
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#endif
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/*----------------------------------------------------------------------*/
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/*
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@ -314,7 +372,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
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gpio_request(gpio + 7, "nCF_SEL");
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gpio_direction_output(gpio + 7, 1);
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/* irlml6401 sustains over 3A, switches 5V in under 8 msec */
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/* irlml6401 switches over 1A, in under 8 msec;
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* now it can be managed by nDRV_VBUS ...
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*/
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setup_usb(500, 8);
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return 0;
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@ -346,13 +406,119 @@ static struct pcf857x_platform_data pcf_data_u35 = {
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* - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
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* - ... newer boards may have more
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*/
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static struct memory_accessor *at24_mem_acc;
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static void at24_setup(struct memory_accessor *mem_acc, void *context)
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{
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DECLARE_MAC_BUF(mac_str);
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char mac_addr[6];
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at24_mem_acc = mem_acc;
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/* Read MAC addr from EEPROM */
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if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
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printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
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print_mac(mac_str, mac_addr));
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}
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}
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static struct at24_platform_data eeprom_info = {
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.byte_len = (256*1024) / 8,
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.page_size = 64,
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.flags = AT24_FLAG_ADDR16,
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.setup = at24_setup,
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};
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int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
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{
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if (at24_mem_acc)
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return at24_mem_acc->read(at24_mem_acc, buf, off, count);
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return -ENODEV;
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}
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EXPORT_SYMBOL(dm6446evm_eeprom_read);
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int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
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{
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if (at24_mem_acc)
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return at24_mem_acc->write(at24_mem_acc, buf, off, count);
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return -ENODEV;
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}
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EXPORT_SYMBOL(dm6446evm_eeprom_write);
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/*
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* MSP430 supports RTC, card detection, input from IR remote, and
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* a bit more. It triggers interrupts on GPIO(7) from pressing
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* buttons on the IR remote, and for card detect switches.
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*/
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static struct i2c_client *dm6446evm_msp;
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static int dm6446evm_msp_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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dm6446evm_msp = client;
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return 0;
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}
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static int dm6446evm_msp_remove(struct i2c_client *client)
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{
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dm6446evm_msp = NULL;
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return 0;
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}
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static const struct i2c_device_id dm6446evm_msp_ids[] = {
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{ "dm6446evm_msp", 0, },
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{ /* end of list */ },
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};
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static struct i2c_driver dm6446evm_msp_driver = {
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.driver.name = "dm6446evm_msp",
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.id_table = dm6446evm_msp_ids,
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.probe = dm6446evm_msp_probe,
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.remove = dm6446evm_msp_remove,
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};
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static int dm6444evm_msp430_get_pins(void)
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{
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static const char txbuf[2] = { 2, 4, };
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char buf[4];
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struct i2c_msg msg[2] = {
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{
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.addr = dm6446evm_msp->addr,
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.flags = 0,
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.len = 2,
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.buf = (void __force *)txbuf,
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},
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{
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.addr = dm6446evm_msp->addr,
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.flags = I2C_M_RD,
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.len = 4,
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.buf = buf,
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},
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};
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int status;
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if (!dm6446evm_msp)
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return -ENXIO;
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/* Command 4 == get input state, returns port 2 and port3 data
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* S Addr W [A] len=2 [A] cmd=4 [A]
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* RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
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*/
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status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
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if (status < 0)
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return status;
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dev_dbg(&dm6446evm_msp->dev,
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"PINS: %02x %02x %02x %02x\n",
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buf[0], buf[1], buf[2], buf[3]);
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return (buf[3] << 8) | buf[2];
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}
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static struct i2c_board_info __initdata i2c_info[] = {
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{
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I2C_BOARD_INFO("dm6446evm_msp", 0x23),
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},
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{
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I2C_BOARD_INFO("pcf8574", 0x38),
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.platform_data = &pcf_data_u2,
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@ -371,7 +537,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
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},
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/* ALSO:
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* - tvl320aic33 audio codec (0x1b)
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* - msp430 microcontroller (0x23)
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* - tvp5146 video decoder (0x5d)
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*/
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};
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@ -387,40 +552,101 @@ static struct davinci_i2c_platform_data i2c_pdata = {
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static void __init evm_init_i2c(void)
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{
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davinci_init_i2c(&i2c_pdata);
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i2c_add_driver(&dm6446evm_msp_driver);
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i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
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}
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static struct platform_device *davinci_evm_devices[] __initdata = {
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#if defined(CONFIG_MTD_PHYSMAP) || \
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defined(CONFIG_MTD_PHYSMAP_MODULE)
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&davinci_evm_norflash_device,
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#endif
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#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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&ide_dev,
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#endif
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&davinci_fb_device,
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&rtc_dev,
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};
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static struct davinci_uart_config uart_config __initdata = {
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.enabled_uarts = (1 << 0),
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};
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static void __init
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davinci_evm_map_io(void)
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{
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davinci_map_common_io();
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dm644x_init();
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}
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static int davinci_phy_fixup(struct phy_device *phydev)
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{
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unsigned int control;
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/* CRITICAL: Fix for increasing PHY signal drive strength for
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* TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
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* signal strength was low causing TX to fail randomly. The
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* fix is to Set bit 11 (Increased MII drive strength) of PHY
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* register 26 (Digital Config register) on this phy. */
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control = phy_read(phydev, 26);
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phy_write(phydev, 26, (control | 0x800));
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return 0;
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}
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#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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#define HAS_ATA 1
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#else
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#define HAS_ATA 0
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#endif
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#if defined(CONFIG_MTD_PHYSMAP) || \
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defined(CONFIG_MTD_PHYSMAP_MODULE)
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#define HAS_NOR 1
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#else
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#define HAS_NOR 0
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#endif
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#if defined(CONFIG_MTD_NAND_DAVINCI) || \
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defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
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#define HAS_NAND 1
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#else
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#define HAS_NAND 0
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#endif
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static __init void davinci_evm_init(void)
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{
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#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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#if defined(CONFIG_MTD_PHYSMAP) || \
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defined(CONFIG_MTD_PHYSMAP_MODULE)
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printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, "
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"but share pins.\n\t Disable IDE for NOR support.\n");
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#endif
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#endif
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struct clk *aemif_clk;
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aemif_clk = clk_get(NULL, "aemif");
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clk_enable(aemif_clk);
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if (HAS_ATA) {
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if (HAS_NAND || HAS_NOR)
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pr_warning("WARNING: both IDE and Flash are "
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"enabled, but they share AEMIF pins.\n"
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"\tDisable IDE for NAND/NOR support.\n");
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davinci_cfg_reg(DM644X_HPIEN_DISABLE);
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davinci_cfg_reg(DM644X_ATAEN);
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davinci_cfg_reg(DM644X_HDIREN);
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platform_device_register(&ide_dev);
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} else if (HAS_NAND || HAS_NOR) {
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davinci_cfg_reg(DM644X_HPIEN_DISABLE);
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davinci_cfg_reg(DM644X_ATAEN_DISABLE);
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/* only one device will be jumpered and detected */
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if (HAS_NAND) {
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platform_device_register(&davinci_evm_nandflash_device);
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evm_leds[7].default_trigger = "nand-disk";
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if (HAS_NOR)
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pr_warning("WARNING: both NAND and NOR flash "
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"are enabled; disable one of them.\n");
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} else if (HAS_NOR)
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platform_device_register(&davinci_evm_norflash_device);
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}
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platform_add_devices(davinci_evm_devices,
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ARRAY_SIZE(davinci_evm_devices));
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evm_init_i2c();
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||||
|
||||
davinci_serial_init(&uart_config);
|
||||
|
||||
/* Register the fixup for PHY on DaVinci */
|
||||
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
|
||||
davinci_phy_fixup);
|
||||
|
||||
}
|
||||
|
||||
static __init void davinci_evm_irq_init(void)
|
||||
|
|
@ -428,7 +654,7 @@ static __init void davinci_evm_irq_init(void)
|
|||
davinci_irq_init();
|
||||
}
|
||||
|
||||
MACHINE_START(DAVINCI_EVM, "DaVinci EVM")
|
||||
MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
|
||||
/* Maintainer: MontaVista Software <source@mvista.com> */
|
||||
.phys_io = IO_PHYS,
|
||||
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,461 @@
|
|||
/*
|
||||
* TI DaVinci DM644x chip specific setup
|
||||
*
|
||||
* Author: Kevin Hilman, Deep Root Systems, LLC
|
||||
*
|
||||
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/dm644x.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/edma.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/psc.h>
|
||||
#include <mach/mux.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "mux.h"
|
||||
|
||||
/*
|
||||
* Device specific clocks
|
||||
*/
|
||||
#define DM644X_REF_FREQ 27000000
|
||||
|
||||
static struct pll_data pll1_data = {
|
||||
.num = 1,
|
||||
.phys_base = DAVINCI_PLL1_BASE,
|
||||
};
|
||||
|
||||
static struct pll_data pll2_data = {
|
||||
.num = 2,
|
||||
.phys_base = DAVINCI_PLL2_BASE,
|
||||
};
|
||||
|
||||
static struct clk ref_clk = {
|
||||
.name = "ref_clk",
|
||||
.rate = DM644X_REF_FREQ,
|
||||
};
|
||||
|
||||
static struct clk pll1_clk = {
|
||||
.name = "pll1",
|
||||
.parent = &ref_clk,
|
||||
.pll_data = &pll1_data,
|
||||
.flags = CLK_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk1 = {
|
||||
.name = "pll1_sysclk1",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV1,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk2 = {
|
||||
.name = "pll1_sysclk2",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV2,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk3 = {
|
||||
.name = "pll1_sysclk3",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV3,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclk5 = {
|
||||
.name = "pll1_sysclk5",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV5,
|
||||
};
|
||||
|
||||
static struct clk pll1_aux_clk = {
|
||||
.name = "pll1_aux_clk",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll1_sysclkbp = {
|
||||
.name = "pll1_sysclkbp",
|
||||
.parent = &pll1_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
.div_reg = BPDIV
|
||||
};
|
||||
|
||||
static struct clk pll2_clk = {
|
||||
.name = "pll2",
|
||||
.parent = &ref_clk,
|
||||
.pll_data = &pll2_data,
|
||||
.flags = CLK_PLL,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclk1 = {
|
||||
.name = "pll2_sysclk1",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV1,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclk2 = {
|
||||
.name = "pll2_sysclk2",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL,
|
||||
.div_reg = PLLDIV2,
|
||||
};
|
||||
|
||||
static struct clk pll2_sysclkbp = {
|
||||
.name = "pll2_sysclkbp",
|
||||
.parent = &pll2_clk,
|
||||
.flags = CLK_PLL | PRE_PLL,
|
||||
.div_reg = BPDIV
|
||||
};
|
||||
|
||||
static struct clk dsp_clk = {
|
||||
.name = "dsp",
|
||||
.parent = &pll1_sysclk1,
|
||||
.lpsc = DAVINCI_LPSC_GEM,
|
||||
.flags = PSC_DSP,
|
||||
.usecount = 1, /* REVISIT how to disable? */
|
||||
};
|
||||
|
||||
static struct clk arm_clk = {
|
||||
.name = "arm",
|
||||
.parent = &pll1_sysclk2,
|
||||
.lpsc = DAVINCI_LPSC_ARM,
|
||||
.flags = ALWAYS_ENABLED,
|
||||
};
|
||||
|
||||
static struct clk vicp_clk = {
|
||||
.name = "vicp",
|
||||
.parent = &pll1_sysclk2,
|
||||
.lpsc = DAVINCI_LPSC_IMCOP,
|
||||
.flags = PSC_DSP,
|
||||
.usecount = 1, /* REVISIT how to disable? */
|
||||
};
|
||||
|
||||
static struct clk vpss_master_clk = {
|
||||
.name = "vpss_master",
|
||||
.parent = &pll1_sysclk3,
|
||||
.lpsc = DAVINCI_LPSC_VPSSMSTR,
|
||||
.flags = CLK_PSC,
|
||||
};
|
||||
|
||||
static struct clk vpss_slave_clk = {
|
||||
.name = "vpss_slave",
|
||||
.parent = &pll1_sysclk3,
|
||||
.lpsc = DAVINCI_LPSC_VPSSSLV,
|
||||
};
|
||||
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART0,
|
||||
};
|
||||
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART1,
|
||||
};
|
||||
|
||||
static struct clk uart2_clk = {
|
||||
.name = "uart2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_UART2,
|
||||
};
|
||||
|
||||
static struct clk emac_clk = {
|
||||
.name = "emac",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
|
||||
};
|
||||
|
||||
static struct clk i2c_clk = {
|
||||
.name = "i2c",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_I2C,
|
||||
};
|
||||
|
||||
static struct clk ide_clk = {
|
||||
.name = "ide",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_ATA,
|
||||
};
|
||||
|
||||
static struct clk asp_clk = {
|
||||
.name = "asp0",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_McBSP,
|
||||
};
|
||||
|
||||
static struct clk mmcsd_clk = {
|
||||
.name = "mmcsd",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_MMC_SD,
|
||||
};
|
||||
|
||||
static struct clk spi_clk = {
|
||||
.name = "spi",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_SPI,
|
||||
};
|
||||
|
||||
static struct clk gpio_clk = {
|
||||
.name = "gpio",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_GPIO,
|
||||
};
|
||||
|
||||
static struct clk usb_clk = {
|
||||
.name = "usb",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_USB,
|
||||
};
|
||||
|
||||
static struct clk vlynq_clk = {
|
||||
.name = "vlynq",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_VLYNQ,
|
||||
};
|
||||
|
||||
static struct clk aemif_clk = {
|
||||
.name = "aemif",
|
||||
.parent = &pll1_sysclk5,
|
||||
.lpsc = DAVINCI_LPSC_AEMIF,
|
||||
};
|
||||
|
||||
static struct clk pwm0_clk = {
|
||||
.name = "pwm0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM0,
|
||||
};
|
||||
|
||||
static struct clk pwm1_clk = {
|
||||
.name = "pwm1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM1,
|
||||
};
|
||||
|
||||
static struct clk pwm2_clk = {
|
||||
.name = "pwm2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_PWM2,
|
||||
};
|
||||
|
||||
static struct clk timer0_clk = {
|
||||
.name = "timer0",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER0,
|
||||
};
|
||||
|
||||
static struct clk timer1_clk = {
|
||||
.name = "timer1",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER1,
|
||||
};
|
||||
|
||||
static struct clk timer2_clk = {
|
||||
.name = "timer2",
|
||||
.parent = &pll1_aux_clk,
|
||||
.lpsc = DAVINCI_LPSC_TIMER2,
|
||||
.usecount = 1, /* REVISIT: why cant' this be disabled? */
|
||||
};
|
||||
|
||||
struct davinci_clk dm644x_clks[] = {
|
||||
CLK(NULL, "ref", &ref_clk),
|
||||
CLK(NULL, "pll1", &pll1_clk),
|
||||
CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
|
||||
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
|
||||
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
|
||||
CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
|
||||
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
||||
CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
|
||||
CLK(NULL, "pll2", &pll2_clk),
|
||||
CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
|
||||
CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
|
||||
CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
|
||||
CLK(NULL, "dsp", &dsp_clk),
|
||||
CLK(NULL, "arm", &arm_clk),
|
||||
CLK(NULL, "vicp", &vicp_clk),
|
||||
CLK(NULL, "vpss_master", &vpss_master_clk),
|
||||
CLK(NULL, "vpss_slave", &vpss_slave_clk),
|
||||
CLK(NULL, "arm", &arm_clk),
|
||||
CLK(NULL, "uart0", &uart0_clk),
|
||||
CLK(NULL, "uart1", &uart1_clk),
|
||||
CLK(NULL, "uart2", &uart2_clk),
|
||||
CLK("davinci_emac.1", NULL, &emac_clk),
|
||||
CLK("i2c_davinci.1", NULL, &i2c_clk),
|
||||
CLK("palm_bk3710", NULL, &ide_clk),
|
||||
CLK("soc-audio.0", NULL, &asp_clk),
|
||||
CLK("davinci_mmc.0", NULL, &mmcsd_clk),
|
||||
CLK(NULL, "spi", &spi_clk),
|
||||
CLK(NULL, "gpio", &gpio_clk),
|
||||
CLK(NULL, "usb", &usb_clk),
|
||||
CLK(NULL, "vlynq", &vlynq_clk),
|
||||
CLK(NULL, "aemif", &aemif_clk),
|
||||
CLK(NULL, "pwm0", &pwm0_clk),
|
||||
CLK(NULL, "pwm1", &pwm1_clk),
|
||||
CLK(NULL, "pwm2", &pwm2_clk),
|
||||
CLK(NULL, "timer0", &timer0_clk),
|
||||
CLK(NULL, "timer1", &timer1_clk),
|
||||
CLK("watchdog", NULL, &timer2_clk),
|
||||
CLK(NULL, NULL, NULL),
|
||||
};
|
||||
|
||||
#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
|
||||
|
||||
static struct resource dm644x_emac_resources[] = {
|
||||
{
|
||||
.start = DM644X_EMAC_BASE,
|
||||
.end = DM644X_EMAC_BASE + 0x47ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_EMACINT,
|
||||
.end = IRQ_EMACINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dm644x_emac_device = {
|
||||
.name = "davinci_emac",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(dm644x_emac_resources),
|
||||
.resource = dm644x_emac_resources,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device specific mux setup
|
||||
*
|
||||
* soc description mux mode mode mux dbg
|
||||
* reg offset mask mode
|
||||
*/
|
||||
static const struct mux_config dm644x_pins[] = {
|
||||
MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
|
||||
MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
|
||||
MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
|
||||
|
||||
MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
|
||||
|
||||
MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
|
||||
|
||||
MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
|
||||
|
||||
MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
|
||||
|
||||
MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
|
||||
|
||||
MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
|
||||
MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
|
||||
|
||||
MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
|
||||
|
||||
MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
|
||||
|
||||
MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
|
||||
|
||||
MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
|
||||
MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
|
||||
MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
|
||||
|
||||
MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
|
||||
|
||||
MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
|
||||
|
||||
MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
|
||||
MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
|
||||
MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
|
||||
MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
|
||||
|
||||
MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
|
||||
|
||||
MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
|
||||
MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
|
||||
};
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static const s8 dma_chan_dm644x_no_event[] = {
|
||||
0, 1, 12, 13, 14,
|
||||
15, 25, 30, 31, 45,
|
||||
46, 47, 55, 56, 57,
|
||||
58, 59, 60, 61, 62,
|
||||
63,
|
||||
-1
|
||||
};
|
||||
|
||||
static struct edma_soc_info dm644x_edma_info = {
|
||||
.n_channel = 64,
|
||||
.n_region = 4,
|
||||
.n_slot = 128,
|
||||
.n_tc = 2,
|
||||
.noevent = dma_chan_dm644x_no_event,
|
||||
};
|
||||
|
||||
static struct resource edma_resources[] = {
|
||||
{
|
||||
.name = "edma_cc",
|
||||
.start = 0x01c00000,
|
||||
.end = 0x01c00000 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_tc0",
|
||||
.start = 0x01c10000,
|
||||
.end = 0x01c10000 + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.name = "edma_tc1",
|
||||
.start = 0x01c10400,
|
||||
.end = 0x01c10400 + SZ_1K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = IRQ_CCINT0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = IRQ_CCERRINT,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
/* not using TC*_ERR */
|
||||
};
|
||||
|
||||
static struct platform_device dm644x_edma_device = {
|
||||
.name = "edma",
|
||||
.id = -1,
|
||||
.dev.platform_data = &dm644x_edma_info,
|
||||
.num_resources = ARRAY_SIZE(edma_resources),
|
||||
.resource = edma_resources,
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
void __init dm644x_init(void)
|
||||
{
|
||||
davinci_clk_init(dm644x_clks);
|
||||
davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
|
||||
}
|
||||
|
||||
static int __init dm644x_init_devices(void)
|
||||
{
|
||||
if (!cpu_is_davinci_dm644x())
|
||||
return 0;
|
||||
|
||||
platform_device_register(&dm644x_edma_device);
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(dm644x_init_devices);
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* DaVinci DM6446 EVM board specific headers
|
||||
*
|
||||
* Author: Kevin Hilman, Deep Root Systems, LLC
|
||||
*
|
||||
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or ifndef.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_DAVINCI_DM6446EVM_H
|
||||
#define _MACH_DAVINCI_DM6446EVM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
|
||||
int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
|
||||
|
||||
#endif
|
||||
|
|
@ -16,6 +16,12 @@ struct sys_timer;
|
|||
|
||||
extern struct sys_timer davinci_timer;
|
||||
|
||||
extern void davinci_irq_init(void);
|
||||
extern void davinci_map_common_io(void);
|
||||
|
||||
/* parameters describe VBUS sourcing for host mode */
|
||||
extern void setup_usb(unsigned mA, unsigned potpgt_msec);
|
||||
|
||||
/* parameters describe VBUS sourcing for host mode */
|
||||
extern void setup_usb(unsigned mA, unsigned potpgt_msec);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* This file contains the processor specific definitions
|
||||
* of the TI DM644x.
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_ARCH_DM644X_H
|
||||
#define __ASM_ARCH_DM644X_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define DM644X_EMAC_BASE (0x01C80000)
|
||||
#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
|
||||
#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
|
||||
#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
|
||||
#define DM644X_EMAC_MDIO_OFFSET (0x4000)
|
||||
#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
|
||||
|
||||
void __init dm644x_init(void);
|
||||
|
||||
#endif /* __ASM_ARCH_DM644X_H */
|
||||
Reference in New Issue