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x86 l3 cache index disable for 2 6 26 fix 

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar 2008-07-28 16:20:08 +02:00
parent a24e8d36f5
commit cdcf772ed1
1 changed files with 20 additions and 19 deletions
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39
arch/x86/kernel/cpu/intel_cacheinfo.c
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@ -1,8 +1,8 @@
/* /*
* Routines to indentify caches on Intel CPU. * Routines to indentify caches on Intel CPU.
* *
* Changes: * Changes:
* Venkatesh Pallipadi : Adding cache identification through cpuid(4) * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
* Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure. * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD. * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
*/ */
@ -136,9 +136,9 @@ struct _cpuid4_info {
}; };
static struct pci_device_id k8_nb_id[] = { static struct pci_device_id k8_nb_id[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
{} {}
}; };
unsigned short num_cache_leaves; unsigned short num_cache_leaves;
@ -190,9 +190,10 @@ static unsigned short assocs[] __cpuinitdata = {
static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 }; static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 };
static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 }; static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 };
static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, static void __cpuinit
union _cpuid4_leaf_ebx *ebx, amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
union _cpuid4_leaf_ecx *ecx) union _cpuid4_leaf_ebx *ebx,
union _cpuid4_leaf_ecx *ecx)
{ {
unsigned dummy; unsigned dummy;
unsigned line_size, lines_per_tag, assoc, size_in_kb; unsigned line_size, lines_per_tag, assoc, size_in_kb;
@ -264,7 +265,7 @@ amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
{ {
if (index < 3) if (index < 3)
return; return;
this_leaf->can_disable = 1; this_leaf->can_disable = 1;
} }
static int static int
@ -474,7 +475,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
/* pointer to _cpuid4_info array (for each cache leaf) */ /* pointer to _cpuid4_info array (for each cache leaf) */
static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info); static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
#define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y])) #define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@ -511,7 +512,7 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
this_leaf = CPUID4_INFO_IDX(cpu, index); this_leaf = CPUID4_INFO_IDX(cpu, index);
for_each_cpu_mask(sibling, this_leaf->shared_cpu_map) { for_each_cpu_mask(sibling, this_leaf->shared_cpu_map) {
sibling_leaf = CPUID4_INFO_IDX(sibling, index); sibling_leaf = CPUID4_INFO_IDX(sibling, index);
cpu_clear(cpu, sibling_leaf->shared_cpu_map); cpu_clear(cpu, sibling_leaf->shared_cpu_map);
} }
} }
@ -593,7 +594,7 @@ struct _index_kobject {
/* pointer to array of kobjects for cpuX/cache/indexY */ /* pointer to array of kobjects for cpuX/cache/indexY */
static DEFINE_PER_CPU(struct _index_kobject *, index_kobject); static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y])) #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
#define show_one_plus(file_name, object, val) \ #define show_one_plus(file_name, object, val) \
static ssize_t show_##file_name \ static ssize_t show_##file_name \
@ -675,7 +676,7 @@ static struct pci_dev *get_k8_northbridge(int node)
if (!dev) if (!dev)
break; break;
} }
return dev; return dev;
} }
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf) static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
@ -736,7 +737,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n"); printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
return -EINVAL; return -EINVAL;
} }
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000); pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd(); wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val); pci_write_config_dword(dev, 0x1BC + index * 4, val);
@ -789,7 +790,7 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
ret = fattr->show ? ret = fattr->show ?
fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
buf) : buf) :
0; 0;
return ret; return ret;
} }
@ -800,9 +801,9 @@ static ssize_t store(struct kobject * kobj, struct attribute * attr,
struct _index_kobject *this_leaf = to_object(kobj); struct _index_kobject *this_leaf = to_object(kobj);
ssize_t ret; ssize_t ret;
ret = fattr->store ? ret = fattr->store ?
fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
buf, count) : buf, count) :
0; 0;
return ret; return ret;
} }