sh: update Solution Engine 7343
updated the following codes for Solution Endine 7343: - fix compile error in arch/sh/boards/se/7343/irq.c - add nor flash physmaps - update defconfig Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshihiro Shimoda
Paul Mundt
parent
a4e1d08491
commit
cafd63b007
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@ -1,202 +1,80 @@
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/*
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* arch/sh/boards/se/7343/irq.c
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* linux/arch/sh/boards/se/7343/irq.c
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/se7343.h>
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#include <asm/se7343.h>
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static void
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disable_intreq_irq(unsigned int irq)
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static void disable_se7343_irq(unsigned int irq)
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{
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int bit = irq - OFFCHIP_IRQ_BASE;
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u16 val;
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val = ctrl_inw(PA_CPLD_IMSK);
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val |= 1 << bit;
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ctrl_outw(val, PA_CPLD_IMSK);
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unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
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ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
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}
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static void
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enable_intreq_irq(unsigned int irq)
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static void enable_se7343_irq(unsigned int irq)
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{
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int bit = irq - OFFCHIP_IRQ_BASE;
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u16 val;
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val = ctrl_inw(PA_CPLD_IMSK);
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val &= ~(1 << bit);
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ctrl_outw(val, PA_CPLD_IMSK);
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unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
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ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
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}
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static void
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mask_and_ack_intreq_irq(unsigned int irq)
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{
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disable_intreq_irq(irq);
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}
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static unsigned int
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startup_intreq_irq(unsigned int irq)
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{
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enable_intreq_irq(irq);
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return 0;
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}
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static void
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shutdown_intreq_irq(unsigned int irq)
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{
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disable_intreq_irq(irq);
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}
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static void
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end_intreq_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_intreq_irq(irq);
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}
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static struct hw_interrupt_type intreq_irq_type = {
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.typename = "FPGA-IRQ",
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.startup = startup_intreq_irq,
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.shutdown = shutdown_intreq_irq,
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.enable = enable_intreq_irq,
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.disable = disable_intreq_irq,
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.ack = mask_and_ack_intreq_irq,
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.end = end_intreq_irq
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static struct irq_chip se7343_irq_chip __read_mostly = {
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.name = "SE7343-FPGA",
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.mask = disable_se7343_irq,
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.unmask = enable_se7343_irq,
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.mask_ack = disable_se7343_irq,
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};
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static void
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make_intreq_irq(unsigned int irq)
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static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].chip = &intreq_irq_type;
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disable_intreq_irq(irq);
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}
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unsigned short intv = ctrl_inw(PA_CPLD_ST);
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struct irq_desc *ext_desc;
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unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
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int
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shmse_irq_demux(int irq)
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{
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int bit;
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volatile u16 val;
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intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
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if (irq == IRQ5_IRQ) {
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/* Read status Register */
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val = ctrl_inw(PA_CPLD_ST);
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bit = ffs(val);
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if (bit != 0)
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return OFFCHIP_IRQ_BASE + bit - 1;
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while (intv) {
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if (intv & 1) {
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ext_desc = irq_desc + ext_irq;
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handle_level_irq(ext_irq, ext_desc);
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}
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intv >>= 1;
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ext_irq++;
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}
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return irq;
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}
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/* IRQ5 is multiplexed between the following sources:
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* 1. PC Card socket
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* 2. Extension slot
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* 3. USB Controller
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* 4. Serial Controller
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*
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* We configure IRQ5 as a cascade IRQ.
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*/
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static struct irqaction irq5 = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "IRQ5-cascade",
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};
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static struct ipr_data se7343_irq5_ipr_map[] = {
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{ IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
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};
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static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
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};
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static struct ipr_data se7343_other_ipr_map[] = {
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{ DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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/* I2C block */
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{ IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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/* SIOF */
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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/* SIU */
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{ SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
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/* VIO interrupt */
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{ CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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/*MFI interrupt*/
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{ MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
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/* LCD controller */
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{ LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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void __init
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init_7343se_IRQ(void)
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void __init init_7343se_IRQ(void)
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{
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/* Setup Multiplexed interrupts */
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ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active
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* low.
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*/
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/* Mask all CPLD controller interrupts */
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ctrl_outw(0x0fff, PA_CPLD_IMSK);
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int i;
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/* PC Card interrupts */
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make_intreq_irq(PC_IRQ0);
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make_intreq_irq(PC_IRQ1);
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make_intreq_irq(PC_IRQ2);
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make_intreq_irq(PC_IRQ3);
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ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
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ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
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/* Extension Slot Interrupts */
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make_intreq_irq(EXT_IRQ0);
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make_intreq_irq(EXT_IRQ1);
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make_intreq_irq(EXT_IRQ2);
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make_intreq_irq(EXT_IRQ3);
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
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set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
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&se7343_irq_chip,
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handle_level_irq, "level");
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/* USB Controller interrupts */
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make_intreq_irq(USB_IRQ0);
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make_intreq_irq(USB_IRQ1);
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/* Serial Controller interrupts */
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make_intreq_irq(UART_IRQ0);
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make_intreq_irq(UART_IRQ1);
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/* Setup all external interrupts to be active low */
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ctrl_outw(0xaaaa, INTC_ICR1);
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make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
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setup_irq(IRQ5_IRQ, &irq5);
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/* Set port control to use IRQ5 */
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*(u16 *)0xA4050108 &= ~0xc;
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make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
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ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
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make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
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ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
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set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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@ -1,10 +1,11 @@
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <asm/machvec.h>
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#include <asm/mach/se7343.h>
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#include <asm/heartbeat.h>
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#include <asm/irq.h>
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void init_7343se_IRQ(void);
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#include <asm/io.h>
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static struct resource smc91x_resources[] = {
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[0] = {
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@ -17,8 +18,8 @@ static struct resource smc91x_resources[] = {
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* shared with other devices via externel
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* interrupt controller in FPGA...
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*/
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.start = EXT_IRQ2,
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.end = EXT_IRQ2,
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.start = SMC_IRQ,
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.end = SMC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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@ -38,16 +39,65 @@ static struct resource heartbeat_resources[] = {
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},
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};
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static struct heartbeat_data heartbeat_data = {
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.regsize = 16,
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.dev = {
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.platform_data = &heartbeat_data,
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},
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.num_resources = ARRAY_SIZE(heartbeat_resources),
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.resource = heartbeat_resources,
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};
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static struct mtd_partition nor_flash_partitions[] = {
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{
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.name = "loader",
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.offset = 0x00000000,
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.size = 128 * 1024,
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},
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{
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.name = "rootfs",
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.offset = MTDPART_OFS_APPEND,
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.size = 31 * 1024 * 1024,
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},
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{
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.name = "data",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data nor_flash_data = {
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.width = 2,
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.parts = nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(nor_flash_partitions),
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};
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static struct resource nor_flash_resources[] = {
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[0] = {
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.start = 0x00000000,
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.end = 0x01ffffff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device nor_flash_device = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &nor_flash_data,
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},
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.num_resources = ARRAY_SIZE(nor_flash_resources),
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.resource = nor_flash_resources,
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};
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static struct platform_device *sh7343se_platform_devices[] __initdata = {
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&smc91x_device,
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&heartbeat_device,
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&nor_flash_device,
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};
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static int __init sh7343se_devices_setup(void)
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@ -55,10 +105,23 @@ static int __init sh7343se_devices_setup(void)
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return platform_add_devices(sh7343se_platform_devices,
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ARRAY_SIZE(sh7343se_platform_devices));
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}
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device_initcall(sh7343se_devices_setup);
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/*
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* Initialize the board
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*/
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static void __init sh7343se_setup(char **cmdline_p)
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{
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device_initcall(sh7343se_devices_setup);
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ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
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ctrl_outl(0x00001001, MSTPCR0);
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ctrl_outl(0x00000000, MSTPCR1);
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ctrl_outl(0xffffbfC0, MSTPCR2); /* LCDC, BEU, CEU, VEU, KEYSC */
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ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
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ctrl_outw(0x0020, PORT_PSELD);
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printk(KERN_INFO "MS7343CP01 Setup...done\n");
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}
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/*
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@ -90,5 +153,4 @@ static struct sh_machine_vector mv_7343se __initmv = {
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.mv_outsl = sh7343se_outsl,
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.mv_init_irq = init_7343se_IRQ,
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.mv_irq_demux = shmse_irq_demux,
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};
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File diff suppressed because it is too large
Load Diff
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@ -59,24 +59,95 @@
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#define PA_LCD1 0xb8000000
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#define PA_LCD2 0xb8800000
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#define PORT_PACR 0xA4050100
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#define PORT_PBCR 0xA4050102
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#define PORT_PCCR 0xA4050104
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#define PORT_PDCR 0xA4050106
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#define PORT_PECR 0xA4050108
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#define PORT_PFCR 0xA405010A
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#define PORT_PGCR 0xA405010C
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#define PORT_PHCR 0xA405010E
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#define PORT_PJCR 0xA4050110
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#define PORT_PKCR 0xA4050112
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#define PORT_PLCR 0xA4050114
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#define PORT_PMCR 0xA4050116
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#define PORT_PNCR 0xA4050118
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#define PORT_PQCR 0xA405011A
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#define PORT_PRCR 0xA405011C
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#define PORT_PSCR 0xA405011E
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#define PORT_PTCR 0xA4050140
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#define PORT_PUCR 0xA4050142
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#define PORT_PVCR 0xA4050144
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#define PORT_PWCR 0xA4050146
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#define PORT_PYCR 0xA4050148
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#define PORT_PZCR 0xA405014A
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#define PORT_PSELA 0xA405014C
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#define PORT_PSELB 0xA405014E
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#define PORT_PSELC 0xA4050150
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#define PORT_PSELD 0xA4050152
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#define PORT_PSELE 0xA4050154
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#define PORT_HIZCRA 0xA4050156
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#define PORT_HIZCRB 0xA4050158
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#define PORT_HIZCRC 0xA405015C
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#define PORT_DRVCR 0xA4050180
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#define PORT_PADR 0xA4050120
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#define PORT_PBDR 0xA4050122
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#define PORT_PCDR 0xA4050124
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#define PORT_PDDR 0xA4050126
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#define PORT_PEDR 0xA4050128
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#define PORT_PFDR 0xA405012A
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#define PORT_PGDR 0xA405012C
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#define PORT_PHDR 0xA405012E
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#define PORT_PJDR 0xA4050130
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#define PORT_PKDR 0xA4050132
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#define PORT_PLDR 0xA4050134
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||||
#define PORT_PMDR 0xA4050136
|
||||
#define PORT_PNDR 0xA4050138
|
||||
#define PORT_PQDR 0xA405013A
|
||||
#define PORT_PRDR 0xA405013C
|
||||
#define PORT_PTDR 0xA4050160
|
||||
#define PORT_PUDR 0xA4050162
|
||||
#define PORT_PVDR 0xA4050164
|
||||
#define PORT_PWDR 0xA4050166
|
||||
#define PORT_PYDR 0xA4050168
|
||||
|
||||
#define MSTPCR0 0xA4150030
|
||||
#define MSTPCR1 0xA4150034
|
||||
#define MSTPCR2 0xA4150038
|
||||
|
||||
#define FPGA_IN 0xb1400000
|
||||
#define FPGA_OUT 0xb1400002
|
||||
|
||||
#define __IO_PREFIX sh7343se
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
/* External Multiplexed interrupts */
|
||||
#define PC_IRQ0 OFFCHIP_IRQ_BASE
|
||||
#define PC_IRQ1 (PC_IRQ0 + 1)
|
||||
#define PC_IRQ2 (PC_IRQ1 + 1)
|
||||
#define PC_IRQ3 (PC_IRQ2 + 1)
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
|
||||
#define EXT_IRQ0 (PC_IRQ3 + 1)
|
||||
#define EXT_IRQ1 (EXT_IRQ0 + 1)
|
||||
#define EXT_IRQ2 (EXT_IRQ1 + 1)
|
||||
#define EXT_IRQ3 (EXT_IRQ2 + 1)
|
||||
#define SE7343_FPGA_IRQ_MRSHPC0 0
|
||||
#define SE7343_FPGA_IRQ_MRSHPC1 1
|
||||
#define SE7343_FPGA_IRQ_MRSHPC2 2
|
||||
#define SE7343_FPGA_IRQ_MRSHPC3 3
|
||||
#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
|
||||
#define SE7343_FPGA_IRQ_USB 8
|
||||
|
||||
#define USB_IRQ0 (EXT_IRQ3 + 1)
|
||||
#define USB_IRQ1 (USB_IRQ0 + 1)
|
||||
#define SE7343_FPGA_IRQ_NR 11
|
||||
#define SE7343_FPGA_IRQ_BASE 120
|
||||
|
||||
#define UART_IRQ0 (USB_IRQ1 + 1)
|
||||
#define UART_IRQ1 (UART_IRQ0 + 1)
|
||||
#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
|
||||
#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
|
||||
#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
|
||||
#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
|
||||
#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
|
||||
#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
|
||||
|
||||
/* arch/sh/boards/se/7343/irq.c */
|
||||
void init_7343se_IRQ(void);
|
||||
|
||||
#endif /* __ASM_SH_HITACHI_SE7343_H */
|
||||
|
|
|
|||
Reference in New Issue