Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, msr/cpuid: Pass the number of minors when unregistering MSR and CPUID drivers. x86: Remove "x86 CPU features in debugfs" (CONFIG_X86_CPU_DEBUG) Revert "x86: ucode-amd: Load ucode-patches once ..." x86: Disable HPET MSI on ATI SB700/SB800 x86: Set hotpluggable nodes in nodes_possible_map
This commit is contained in:
commit
caf0801e0c
13 changed files with 40 additions and 865 deletions
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@ -989,12 +989,6 @@ config X86_CPUID
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with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
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/dev/cpu/31/cpuid.
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config X86_CPU_DEBUG
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tristate "/sys/kernel/debug/x86/cpu/* - CPU Debug support"
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---help---
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If you select this option, this will provide various x86 CPUs
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information through debugfs.
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choice
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prompt "High Memory Support"
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default HIGHMEM4G if !X86_NUMAQ
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@ -1,127 +0,0 @@
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#ifndef _ASM_X86_CPU_DEBUG_H
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#define _ASM_X86_CPU_DEBUG_H
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/*
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* CPU x86 architecture debug
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*
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* Copyright(C) 2009 Jaswinder Singh Rajput
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*/
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/* Register flags */
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enum cpu_debug_bit {
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/* Model Specific Registers (MSRs) */
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CPU_MC_BIT, /* Machine Check */
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CPU_MONITOR_BIT, /* Monitor */
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CPU_TIME_BIT, /* Time */
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CPU_PMC_BIT, /* Performance Monitor */
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CPU_PLATFORM_BIT, /* Platform */
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CPU_APIC_BIT, /* APIC */
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CPU_POWERON_BIT, /* Power-on */
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CPU_CONTROL_BIT, /* Control */
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CPU_FEATURES_BIT, /* Features control */
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CPU_LBRANCH_BIT, /* Last Branch */
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CPU_BIOS_BIT, /* BIOS */
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CPU_FREQ_BIT, /* Frequency */
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CPU_MTTR_BIT, /* MTRR */
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CPU_PERF_BIT, /* Performance */
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CPU_CACHE_BIT, /* Cache */
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CPU_SYSENTER_BIT, /* Sysenter */
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CPU_THERM_BIT, /* Thermal */
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CPU_MISC_BIT, /* Miscellaneous */
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CPU_DEBUG_BIT, /* Debug */
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CPU_PAT_BIT, /* PAT */
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CPU_VMX_BIT, /* VMX */
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CPU_CALL_BIT, /* System Call */
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CPU_BASE_BIT, /* BASE Address */
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CPU_VER_BIT, /* Version ID */
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CPU_CONF_BIT, /* Configuration */
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CPU_SMM_BIT, /* System mgmt mode */
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CPU_SVM_BIT, /*Secure Virtual Machine*/
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CPU_OSVM_BIT, /* OS-Visible Workaround*/
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/* Standard Registers */
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CPU_TSS_BIT, /* Task Stack Segment */
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CPU_CR_BIT, /* Control Registers */
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CPU_DT_BIT, /* Descriptor Table */
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/* End of Registers flags */
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CPU_REG_ALL_BIT, /* Select all Registers */
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};
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#define CPU_REG_ALL (~0) /* Select all Registers */
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#define CPU_MC (1 << CPU_MC_BIT)
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#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
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#define CPU_TIME (1 << CPU_TIME_BIT)
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#define CPU_PMC (1 << CPU_PMC_BIT)
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#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
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#define CPU_APIC (1 << CPU_APIC_BIT)
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#define CPU_POWERON (1 << CPU_POWERON_BIT)
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#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
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#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
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#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
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#define CPU_BIOS (1 << CPU_BIOS_BIT)
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#define CPU_FREQ (1 << CPU_FREQ_BIT)
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#define CPU_MTRR (1 << CPU_MTTR_BIT)
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#define CPU_PERF (1 << CPU_PERF_BIT)
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#define CPU_CACHE (1 << CPU_CACHE_BIT)
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#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
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#define CPU_THERM (1 << CPU_THERM_BIT)
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#define CPU_MISC (1 << CPU_MISC_BIT)
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#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
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#define CPU_PAT (1 << CPU_PAT_BIT)
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#define CPU_VMX (1 << CPU_VMX_BIT)
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#define CPU_CALL (1 << CPU_CALL_BIT)
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#define CPU_BASE (1 << CPU_BASE_BIT)
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#define CPU_VER (1 << CPU_VER_BIT)
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#define CPU_CONF (1 << CPU_CONF_BIT)
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#define CPU_SMM (1 << CPU_SMM_BIT)
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#define CPU_SVM (1 << CPU_SVM_BIT)
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#define CPU_OSVM (1 << CPU_OSVM_BIT)
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#define CPU_TSS (1 << CPU_TSS_BIT)
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#define CPU_CR (1 << CPU_CR_BIT)
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#define CPU_DT (1 << CPU_DT_BIT)
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/* Register file flags */
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enum cpu_file_bit {
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CPU_INDEX_BIT, /* index */
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CPU_VALUE_BIT, /* value */
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};
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#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
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#define MAX_CPU_FILES 512
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struct cpu_private {
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unsigned cpu;
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unsigned type;
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unsigned reg;
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unsigned file;
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};
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struct cpu_debug_base {
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char *name; /* Register name */
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unsigned flag; /* Register flag */
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unsigned write; /* Register write flag */
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};
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/*
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* Currently it looks similar to cpu_debug_base but once we add more files
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* cpu_file_base will go in different direction
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*/
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struct cpu_file_base {
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char *name; /* Register file name */
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unsigned flag; /* Register file flag */
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unsigned write; /* Register write flag */
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};
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struct cpu_cpuX_base {
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struct dentry *dentry; /* Register dentry */
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int init; /* Register index file */
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};
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struct cpu_debug_range {
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unsigned min; /* Register range min */
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unsigned max; /* Register range max */
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unsigned flag; /* Supported flags */
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};
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#endif /* _ASM_X86_CPU_DEBUG_H */
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@ -67,6 +67,7 @@ extern unsigned long hpet_address;
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extern unsigned long force_hpet_address;
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extern u8 hpet_blockid;
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extern int hpet_force_user;
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extern u8 hpet_msi_disable;
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extern int is_hpet_enabled(void);
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extern int hpet_enable(void);
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extern void hpet_disable(void);
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@ -12,8 +12,6 @@ struct device;
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enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
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struct microcode_ops {
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void (*init)(struct device *device);
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void (*fini)(void);
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enum ucode_state (*request_microcode_user) (int cpu,
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const void __user *buf, size_t size);
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@ -19,8 +19,6 @@ obj-y += vmware.o hypervisor.o sched.o
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obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o
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obj-$(CONFIG_X86_64) += bugs_64.o
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obj-$(CONFIG_X86_CPU_DEBUG) += cpu_debug.o
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obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
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obj-$(CONFIG_CPU_SUP_AMD) += amd.o
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obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
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@ -1,688 +0,0 @@
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/*
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* CPU x86 architecture debug code
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*
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* Copyright(C) 2009 Jaswinder Singh Rajput
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/interrupt.h>
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#include <linux/compiler.h>
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#include <linux/seq_file.h>
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#include <linux/debugfs.h>
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#include <linux/kprobes.h>
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#include <linux/uaccess.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/signal.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <asm/cpu_debug.h>
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#include <asm/paravirt.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/apic.h>
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#include <asm/desc.h>
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static DEFINE_PER_CPU(struct cpu_cpuX_base [CPU_REG_ALL_BIT], cpud_arr);
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static DEFINE_PER_CPU(struct cpu_private * [MAX_CPU_FILES], cpud_priv_arr);
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static DEFINE_PER_CPU(int, cpud_priv_count);
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static DEFINE_MUTEX(cpu_debug_lock);
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static struct dentry *cpu_debugfs_dir;
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static struct cpu_debug_base cpu_base[] = {
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{ "mc", CPU_MC, 0 },
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{ "monitor", CPU_MONITOR, 0 },
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{ "time", CPU_TIME, 0 },
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{ "pmc", CPU_PMC, 1 },
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{ "platform", CPU_PLATFORM, 0 },
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{ "apic", CPU_APIC, 0 },
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{ "poweron", CPU_POWERON, 0 },
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{ "control", CPU_CONTROL, 0 },
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{ "features", CPU_FEATURES, 0 },
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{ "lastbranch", CPU_LBRANCH, 0 },
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{ "bios", CPU_BIOS, 0 },
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{ "freq", CPU_FREQ, 0 },
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{ "mtrr", CPU_MTRR, 0 },
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{ "perf", CPU_PERF, 0 },
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{ "cache", CPU_CACHE, 0 },
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{ "sysenter", CPU_SYSENTER, 0 },
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{ "therm", CPU_THERM, 0 },
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{ "misc", CPU_MISC, 0 },
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{ "debug", CPU_DEBUG, 0 },
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{ "pat", CPU_PAT, 0 },
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{ "vmx", CPU_VMX, 0 },
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{ "call", CPU_CALL, 0 },
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{ "base", CPU_BASE, 0 },
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{ "ver", CPU_VER, 0 },
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{ "conf", CPU_CONF, 0 },
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{ "smm", CPU_SMM, 0 },
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{ "svm", CPU_SVM, 0 },
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{ "osvm", CPU_OSVM, 0 },
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{ "tss", CPU_TSS, 0 },
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{ "cr", CPU_CR, 0 },
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{ "dt", CPU_DT, 0 },
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{ "registers", CPU_REG_ALL, 0 },
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};
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static struct cpu_file_base cpu_file[] = {
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{ "index", CPU_REG_ALL, 0 },
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{ "value", CPU_REG_ALL, 1 },
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};
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/* CPU Registers Range */
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static struct cpu_debug_range cpu_reg_range[] = {
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{ 0x00000000, 0x00000001, CPU_MC, },
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{ 0x00000006, 0x00000007, CPU_MONITOR, },
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{ 0x00000010, 0x00000010, CPU_TIME, },
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{ 0x00000011, 0x00000013, CPU_PMC, },
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{ 0x00000017, 0x00000017, CPU_PLATFORM, },
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{ 0x0000001B, 0x0000001B, CPU_APIC, },
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{ 0x0000002A, 0x0000002B, CPU_POWERON, },
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{ 0x0000002C, 0x0000002C, CPU_FREQ, },
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{ 0x0000003A, 0x0000003A, CPU_CONTROL, },
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{ 0x00000040, 0x00000047, CPU_LBRANCH, },
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{ 0x00000060, 0x00000067, CPU_LBRANCH, },
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{ 0x00000079, 0x00000079, CPU_BIOS, },
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{ 0x00000088, 0x0000008A, CPU_CACHE, },
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{ 0x0000008B, 0x0000008B, CPU_BIOS, },
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{ 0x0000009B, 0x0000009B, CPU_MONITOR, },
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{ 0x000000C1, 0x000000C4, CPU_PMC, },
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{ 0x000000CD, 0x000000CD, CPU_FREQ, },
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{ 0x000000E7, 0x000000E8, CPU_PERF, },
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{ 0x000000FE, 0x000000FE, CPU_MTRR, },
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{ 0x00000116, 0x0000011E, CPU_CACHE, },
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{ 0x00000174, 0x00000176, CPU_SYSENTER, },
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{ 0x00000179, 0x0000017B, CPU_MC, },
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{ 0x00000186, 0x00000189, CPU_PMC, },
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{ 0x00000198, 0x00000199, CPU_PERF, },
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{ 0x0000019A, 0x0000019A, CPU_TIME, },
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{ 0x0000019B, 0x0000019D, CPU_THERM, },
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{ 0x000001A0, 0x000001A0, CPU_MISC, },
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{ 0x000001C9, 0x000001C9, CPU_LBRANCH, },
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{ 0x000001D7, 0x000001D8, CPU_LBRANCH, },
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{ 0x000001D9, 0x000001D9, CPU_DEBUG, },
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{ 0x000001DA, 0x000001E0, CPU_LBRANCH, },
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{ 0x00000200, 0x0000020F, CPU_MTRR, },
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{ 0x00000250, 0x00000250, CPU_MTRR, },
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{ 0x00000258, 0x00000259, CPU_MTRR, },
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{ 0x00000268, 0x0000026F, CPU_MTRR, },
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{ 0x00000277, 0x00000277, CPU_PAT, },
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{ 0x000002FF, 0x000002FF, CPU_MTRR, },
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{ 0x00000300, 0x00000311, CPU_PMC, },
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{ 0x00000345, 0x00000345, CPU_PMC, },
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{ 0x00000360, 0x00000371, CPU_PMC, },
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{ 0x0000038D, 0x00000390, CPU_PMC, },
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{ 0x000003A0, 0x000003BE, CPU_PMC, },
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{ 0x000003C0, 0x000003CD, CPU_PMC, },
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{ 0x000003E0, 0x000003E1, CPU_PMC, },
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{ 0x000003F0, 0x000003F2, CPU_PMC, },
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{ 0x00000400, 0x00000417, CPU_MC, },
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{ 0x00000480, 0x0000048B, CPU_VMX, },
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{ 0x00000600, 0x00000600, CPU_DEBUG, },
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{ 0x00000680, 0x0000068F, CPU_LBRANCH, },
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{ 0x000006C0, 0x000006CF, CPU_LBRANCH, },
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{ 0x000107CC, 0x000107D3, CPU_PMC, },
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{ 0xC0000080, 0xC0000080, CPU_FEATURES, },
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{ 0xC0000081, 0xC0000084, CPU_CALL, },
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{ 0xC0000100, 0xC0000102, CPU_BASE, },
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{ 0xC0000103, 0xC0000103, CPU_TIME, },
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{ 0xC0010000, 0xC0010007, CPU_PMC, },
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{ 0xC0010010, 0xC0010010, CPU_CONF, },
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{ 0xC0010015, 0xC0010015, CPU_CONF, },
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{ 0xC0010016, 0xC001001A, CPU_MTRR, },
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{ 0xC001001D, 0xC001001D, CPU_MTRR, },
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{ 0xC001001F, 0xC001001F, CPU_CONF, },
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{ 0xC0010030, 0xC0010035, CPU_BIOS, },
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{ 0xC0010044, 0xC0010048, CPU_MC, },
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{ 0xC0010050, 0xC0010056, CPU_SMM, },
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{ 0xC0010058, 0xC0010058, CPU_CONF, },
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{ 0xC0010060, 0xC0010060, CPU_CACHE, },
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{ 0xC0010061, 0xC0010068, CPU_SMM, },
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{ 0xC0010069, 0xC001006B, CPU_SMM, },
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{ 0xC0010070, 0xC0010071, CPU_SMM, },
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{ 0xC0010111, 0xC0010113, CPU_SMM, },
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{ 0xC0010114, 0xC0010118, CPU_SVM, },
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{ 0xC0010140, 0xC0010141, CPU_OSVM, },
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{ 0xC0011022, 0xC0011023, CPU_CONF, },
|
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};
|
||||
|
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static int is_typeflag_valid(unsigned cpu, unsigned flag)
|
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{
|
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int i;
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|
||||
/* Standard Registers should be always valid */
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if (flag >= CPU_TSS)
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return 1;
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||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
|
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if (cpu_reg_range[i].flag == flag)
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return 1;
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}
|
||||
|
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/* Invalid */
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return 0;
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}
|
||||
|
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static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max,
|
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int index, unsigned flag)
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{
|
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if (cpu_reg_range[index].flag == flag) {
|
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*min = cpu_reg_range[index].min;
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*max = cpu_reg_range[index].max;
|
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} else
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*max = 0;
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||||
|
||||
return *max;
|
||||
}
|
||||
|
||||
/* This function can also be called with seq = NULL for printk */
|
||||
static void print_cpu_data(struct seq_file *seq, unsigned type,
|
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u32 low, u32 high)
|
||||
{
|
||||
struct cpu_private *priv;
|
||||
u64 val = high;
|
||||
|
||||
if (seq) {
|
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priv = seq->private;
|
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if (priv->file) {
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val = (val << 32) | low;
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seq_printf(seq, "0x%llx\n", val);
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} else
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seq_printf(seq, " %08x: %08x_%08x\n",
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type, high, low);
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} else
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printk(KERN_INFO " %08x: %08x_%08x\n", type, high, low);
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}
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||||
|
||||
/* This function can also be called with seq = NULL for printk */
|
||||
static void print_msr(struct seq_file *seq, unsigned cpu, unsigned flag)
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{
|
||||
unsigned msr, msr_min, msr_max;
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||||
struct cpu_private *priv;
|
||||
u32 low, high;
|
||||
int i;
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||||
|
||||
if (seq) {
|
||||
priv = seq->private;
|
||||
if (priv->file) {
|
||||
if (!rdmsr_safe_on_cpu(priv->cpu, priv->reg,
|
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&low, &high))
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print_cpu_data(seq, priv->reg, low, high);
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return;
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||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
|
||||
if (!get_cpu_range(cpu, &msr_min, &msr_max, i, flag))
|
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continue;
|
||||
|
||||
for (msr = msr_min; msr <= msr_max; msr++) {
|
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if (rdmsr_safe_on_cpu(cpu, msr, &low, &high))
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continue;
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print_cpu_data(seq, msr, low, high);
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||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void print_tss(void *arg)
|
||||
{
|
||||
struct pt_regs *regs = task_pt_regs(current);
|
||||
struct seq_file *seq = arg;
|
||||
unsigned int seg;
|
||||
|
||||
seq_printf(seq, " RAX\t: %016lx\n", regs->ax);
|
||||
seq_printf(seq, " RBX\t: %016lx\n", regs->bx);
|
||||
seq_printf(seq, " RCX\t: %016lx\n", regs->cx);
|
||||
seq_printf(seq, " RDX\t: %016lx\n", regs->dx);
|
||||
|
||||
seq_printf(seq, " RSI\t: %016lx\n", regs->si);
|
||||
seq_printf(seq, " RDI\t: %016lx\n", regs->di);
|
||||
seq_printf(seq, " RBP\t: %016lx\n", regs->bp);
|
||||
seq_printf(seq, " ESP\t: %016lx\n", regs->sp);
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
seq_printf(seq, " R08\t: %016lx\n", regs->r8);
|
||||
seq_printf(seq, " R09\t: %016lx\n", regs->r9);
|
||||
seq_printf(seq, " R10\t: %016lx\n", regs->r10);
|
||||
seq_printf(seq, " R11\t: %016lx\n", regs->r11);
|
||||
seq_printf(seq, " R12\t: %016lx\n", regs->r12);
|
||||
seq_printf(seq, " R13\t: %016lx\n", regs->r13);
|
||||
seq_printf(seq, " R14\t: %016lx\n", regs->r14);
|
||||
seq_printf(seq, " R15\t: %016lx\n", regs->r15);
|
||||
#endif
|
||||
|
||||
asm("movl %%cs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " CS\t: %04x\n", seg);
|
||||
asm("movl %%ds,%0" : "=r" (seg));
|
||||
seq_printf(seq, " DS\t: %04x\n", seg);
|
||||
seq_printf(seq, " SS\t: %04lx\n", regs->ss & 0xffff);
|
||||
asm("movl %%es,%0" : "=r" (seg));
|
||||
seq_printf(seq, " ES\t: %04x\n", seg);
|
||||
asm("movl %%fs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " FS\t: %04x\n", seg);
|
||||
asm("movl %%gs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " GS\t: %04x\n", seg);
|
||||
|
||||
seq_printf(seq, " EFLAGS\t: %016lx\n", regs->flags);
|
||||
|
||||
seq_printf(seq, " EIP\t: %016lx\n", regs->ip);
|
||||
}
|
||||
|
||||
static void print_cr(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
|
||||
seq_printf(seq, " cr0\t: %016lx\n", read_cr0());
|
||||
seq_printf(seq, " cr2\t: %016lx\n", read_cr2());
|
||||
seq_printf(seq, " cr3\t: %016lx\n", read_cr3());
|
||||
seq_printf(seq, " cr4\t: %016lx\n", read_cr4_safe());
|
||||
#ifdef CONFIG_X86_64
|
||||
seq_printf(seq, " cr8\t: %016lx\n", read_cr8());
|
||||
#endif
|
||||
}
|
||||
|
||||
static void print_desc_ptr(char *str, struct seq_file *seq, struct desc_ptr dt)
|
||||
{
|
||||
seq_printf(seq, " %s\t: %016llx\n", str, (u64)(dt.address | dt.size));
|
||||
}
|
||||
|
||||
static void print_dt(void *seq)
|
||||
{
|
||||
struct desc_ptr dt;
|
||||
unsigned long ldt;
|
||||
|
||||
/* IDT */
|
||||
store_idt((struct desc_ptr *)&dt);
|
||||
print_desc_ptr("IDT", seq, dt);
|
||||
|
||||
/* GDT */
|
||||
store_gdt((struct desc_ptr *)&dt);
|
||||
print_desc_ptr("GDT", seq, dt);
|
||||
|
||||
/* LDT */
|
||||
store_ldt(ldt);
|
||||
seq_printf(seq, " LDT\t: %016lx\n", ldt);
|
||||
|
||||
/* TR */
|
||||
store_tr(ldt);
|
||||
seq_printf(seq, " TR\t: %016lx\n", ldt);
|
||||
}
|
||||
|
||||
static void print_dr(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
unsigned long dr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
/* Ignore db4, db5 */
|
||||
if ((i == 4) || (i == 5))
|
||||
continue;
|
||||
get_debugreg(dr, i);
|
||||
seq_printf(seq, " dr%d\t: %016lx\n", i, dr);
|
||||
}
|
||||
|
||||
seq_printf(seq, "\n MSR\t:\n");
|
||||
}
|
||||
|
||||
static void print_apic(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
seq_printf(seq, " LAPIC\t:\n");
|
||||
seq_printf(seq, " ID\t\t: %08x\n", apic_read(APIC_ID) >> 24);
|
||||
seq_printf(seq, " LVR\t\t: %08x\n", apic_read(APIC_LVR));
|
||||
seq_printf(seq, " TASKPRI\t: %08x\n", apic_read(APIC_TASKPRI));
|
||||
seq_printf(seq, " ARBPRI\t\t: %08x\n", apic_read(APIC_ARBPRI));
|
||||
seq_printf(seq, " PROCPRI\t: %08x\n", apic_read(APIC_PROCPRI));
|
||||
seq_printf(seq, " LDR\t\t: %08x\n", apic_read(APIC_LDR));
|
||||
seq_printf(seq, " DFR\t\t: %08x\n", apic_read(APIC_DFR));
|
||||
seq_printf(seq, " SPIV\t\t: %08x\n", apic_read(APIC_SPIV));
|
||||
seq_printf(seq, " ISR\t\t: %08x\n", apic_read(APIC_ISR));
|
||||
seq_printf(seq, " ESR\t\t: %08x\n", apic_read(APIC_ESR));
|
||||
seq_printf(seq, " ICR\t\t: %08x\n", apic_read(APIC_ICR));
|
||||
seq_printf(seq, " ICR2\t\t: %08x\n", apic_read(APIC_ICR2));
|
||||
seq_printf(seq, " LVTT\t\t: %08x\n", apic_read(APIC_LVTT));
|
||||
seq_printf(seq, " LVTTHMR\t: %08x\n", apic_read(APIC_LVTTHMR));
|
||||
seq_printf(seq, " LVTPC\t\t: %08x\n", apic_read(APIC_LVTPC));
|
||||
seq_printf(seq, " LVT0\t\t: %08x\n", apic_read(APIC_LVT0));
|
||||
seq_printf(seq, " LVT1\t\t: %08x\n", apic_read(APIC_LVT1));
|
||||
seq_printf(seq, " LVTERR\t\t: %08x\n", apic_read(APIC_LVTERR));
|
||||
seq_printf(seq, " TMICT\t\t: %08x\n", apic_read(APIC_TMICT));
|
||||
seq_printf(seq, " TMCCT\t\t: %08x\n", apic_read(APIC_TMCCT));
|
||||
seq_printf(seq, " TDCR\t\t: %08x\n", apic_read(APIC_TDCR));
|
||||
if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
|
||||
unsigned int i, v, maxeilvt;
|
||||
|
||||
v = apic_read(APIC_EFEAT);
|
||||
maxeilvt = (v >> 16) & 0xff;
|
||||
seq_printf(seq, " EFEAT\t\t: %08x\n", v);
|
||||
seq_printf(seq, " ECTRL\t\t: %08x\n", apic_read(APIC_ECTRL));
|
||||
|
||||
for (i = 0; i < maxeilvt; i++) {
|
||||
v = apic_read(APIC_EILVTn(i));
|
||||
seq_printf(seq, " EILVT%d\t\t: %08x\n", i, v);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_X86_LOCAL_APIC */
|
||||
seq_printf(seq, "\n MSR\t:\n");
|
||||
}
|
||||
|
||||
static int cpu_seq_show(struct seq_file *seq, void *v)
|
||||
{
|
||||
struct cpu_private *priv = seq->private;
|
||||
|
||||
if (priv == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
switch (cpu_base[priv->type].flag) {
|
||||
case CPU_TSS:
|
||||
smp_call_function_single(priv->cpu, print_tss, seq, 1);
|
||||
break;
|
||||
case CPU_CR:
|
||||
smp_call_function_single(priv->cpu, print_cr, seq, 1);
|
||||
break;
|
||||
case CPU_DT:
|
||||
smp_call_function_single(priv->cpu, print_dt, seq, 1);
|
||||
break;
|
||||
case CPU_DEBUG:
|
||||
if (priv->file == CPU_INDEX_BIT)
|
||||
smp_call_function_single(priv->cpu, print_dr, seq, 1);
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
case CPU_APIC:
|
||||
if (priv->file == CPU_INDEX_BIT)
|
||||
smp_call_function_single(priv->cpu, print_apic, seq, 1);
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
|
||||
default:
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
}
|
||||
seq_printf(seq, "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *cpu_seq_start(struct seq_file *seq, loff_t *pos)
|
||||
{
|
||||
if (*pos == 0) /* One time is enough ;-) */
|
||||
return seq;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void *cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
|
||||
{
|
||||
(*pos)++;
|
||||
|
||||
return cpu_seq_start(seq, pos);
|
||||
}
|
||||
|
||||
static void cpu_seq_stop(struct seq_file *seq, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct seq_operations cpu_seq_ops = {
|
||||
.start = cpu_seq_start,
|
||||
.next = cpu_seq_next,
|
||||
.stop = cpu_seq_stop,
|
||||
.show = cpu_seq_show,
|
||||
};
|
||||
|
||||
static int cpu_seq_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct cpu_private *priv = inode->i_private;
|
||||
struct seq_file *seq;
|
||||
int err;
|
||||
|
||||
err = seq_open(file, &cpu_seq_ops);
|
||||
if (!err) {
|
||||
seq = file->private_data;
|
||||
seq->private = priv;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int write_msr(struct cpu_private *priv, u64 val)
|
||||
{
|
||||
u32 low, high;
|
||||
|
||||
high = (val >> 32) & 0xffffffff;
|
||||
low = val & 0xffffffff;
|
||||
|
||||
if (!wrmsr_safe_on_cpu(priv->cpu, priv->reg, low, high))
|
||||
return 0;
|
||||
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
static int write_cpu_register(struct cpu_private *priv, const char *buf)
|
||||
{
|
||||
int ret = -EPERM;
|
||||
u64 val;
|
||||
|
||||
ret = strict_strtoull(buf, 0, &val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Supporting only MSRs */
|
||||
if (priv->type < CPU_TSS_BIT)
|
||||
return write_msr(priv, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t cpu_write(struct file *file, const char __user *ubuf,
|
||||
size_t count, loff_t *off)
|
||||
{
|
||||
struct seq_file *seq = file->private_data;
|
||||
struct cpu_private *priv = seq->private;
|
||||
char buf[19];
|
||||
|
||||
if ((priv == NULL) || (count >= sizeof(buf)))
|
||||
return -EINVAL;
|
||||
|
||||
if (copy_from_user(&buf, ubuf, count))
|
||||
return -EFAULT;
|
||||
|
||||
buf[count] = 0;
|
||||
|
||||
if ((cpu_base[priv->type].write) && (cpu_file[priv->file].write))
|
||||
if (!write_cpu_register(priv, buf))
|
||||
return count;
|
||||
|
||||
return -EACCES;
|
||||
}
|
||||
|
||||
static const struct file_operations cpu_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = cpu_seq_open,
|
||||
.read = seq_read,
|
||||
.write = cpu_write,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
};
|
||||
|
||||
static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
|
||||
unsigned file, struct dentry *dentry)
|
||||
{
|
||||
struct cpu_private *priv = NULL;
|
||||
|
||||
/* Already intialized */
|
||||
if (file == CPU_INDEX_BIT)
|
||||
if (per_cpu(cpud_arr[type].init, cpu))
|
||||
return 0;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (priv == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->cpu = cpu;
|
||||
priv->type = type;
|
||||
priv->reg = reg;
|
||||
priv->file = file;
|
||||
mutex_lock(&cpu_debug_lock);
|
||||
per_cpu(cpud_priv_arr[type], cpu) = priv;
|
||||
per_cpu(cpud_priv_count, cpu)++;
|
||||
mutex_unlock(&cpu_debug_lock);
|
||||
|
||||
if (file)
|
||||
debugfs_create_file(cpu_file[file].name, S_IRUGO,
|
||||
dentry, (void *)priv, &cpu_fops);
|
||||
else {
|
||||
debugfs_create_file(cpu_base[type].name, S_IRUGO,
|
||||
per_cpu(cpud_arr[type].dentry, cpu),
|
||||
(void *)priv, &cpu_fops);
|
||||
mutex_lock(&cpu_debug_lock);
|
||||
per_cpu(cpud_arr[type].init, cpu) = 1;
|
||||
mutex_unlock(&cpu_debug_lock);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpu_init_regfiles(unsigned cpu, unsigned int type, unsigned reg,
|
||||
struct dentry *dentry)
|
||||
{
|
||||
unsigned file;
|
||||
int err = 0;
|
||||
|
||||
for (file = 0; file < ARRAY_SIZE(cpu_file); file++) {
|
||||
err = cpu_create_file(cpu, type, reg, file, dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_msr(unsigned cpu, unsigned type, struct dentry *dentry)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
unsigned reg, reg_min, reg_max;
|
||||
int i, err = 0;
|
||||
char reg_dir[12];
|
||||
u32 low, high;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_reg_range); i++) {
|
||||
if (!get_cpu_range(cpu, ®_min, ®_max, i,
|
||||
cpu_base[type].flag))
|
||||
continue;
|
||||
|
||||
for (reg = reg_min; reg <= reg_max; reg++) {
|
||||
if (rdmsr_safe_on_cpu(cpu, reg, &low, &high))
|
||||
continue;
|
||||
|
||||
sprintf(reg_dir, "0x%x", reg);
|
||||
cpu_dentry = debugfs_create_dir(reg_dir, dentry);
|
||||
err = cpu_init_regfiles(cpu, type, reg, cpu_dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_allreg(unsigned cpu, struct dentry *dentry)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
unsigned type;
|
||||
int err = 0;
|
||||
|
||||
for (type = 0; type < ARRAY_SIZE(cpu_base) - 1; type++) {
|
||||
if (!is_typeflag_valid(cpu, cpu_base[type].flag))
|
||||
continue;
|
||||
cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry);
|
||||
per_cpu(cpud_arr[type].dentry, cpu) = cpu_dentry;
|
||||
|
||||
if (type < CPU_TSS_BIT)
|
||||
err = cpu_init_msr(cpu, type, cpu_dentry);
|
||||
else
|
||||
err = cpu_create_file(cpu, type, 0, CPU_INDEX_BIT,
|
||||
cpu_dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_cpu(void)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
struct cpuinfo_x86 *cpui;
|
||||
char cpu_dir[12];
|
||||
unsigned cpu;
|
||||
int err = 0;
|
||||
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
|
||||
cpui = &cpu_data(cpu);
|
||||
if (!cpu_has(cpui, X86_FEATURE_MSR))
|
||||
continue;
|
||||
|
||||
sprintf(cpu_dir, "cpu%d", cpu);
|
||||
cpu_dentry = debugfs_create_dir(cpu_dir, cpu_debugfs_dir);
|
||||
err = cpu_init_allreg(cpu, cpu_dentry);
|
||||
|
||||
pr_info("cpu%d(%d) debug files %d\n",
|
||||
cpu, nr_cpu_ids, per_cpu(cpud_priv_count, cpu));
|
||||
if (per_cpu(cpud_priv_count, cpu) > MAX_CPU_FILES) {
|
||||
pr_err("Register files count %d exceeds limit %d\n",
|
||||
per_cpu(cpud_priv_count, cpu), MAX_CPU_FILES);
|
||||
per_cpu(cpud_priv_count, cpu) = MAX_CPU_FILES;
|
||||
err = -ENFILE;
|
||||
}
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init cpu_debug_init(void)
|
||||
{
|
||||
cpu_debugfs_dir = debugfs_create_dir("cpu", arch_debugfs_dir);
|
||||
|
||||
return cpu_init_cpu();
|
||||
}
|
||||
|
||||
static void __exit cpu_debug_exit(void)
|
||||
{
|
||||
int i, cpu;
|
||||
|
||||
if (cpu_debugfs_dir)
|
||||
debugfs_remove_recursive(cpu_debugfs_dir);
|
||||
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
|
||||
for (i = 0; i < per_cpu(cpud_priv_count, cpu); i++)
|
||||
kfree(per_cpu(cpud_priv_arr[i], cpu));
|
||||
}
|
||||
|
||||
module_init(cpu_debug_init);
|
||||
module_exit(cpu_debug_exit);
|
||||
|
||||
MODULE_AUTHOR("Jaswinder Singh Rajput");
|
||||
MODULE_DESCRIPTION("CPU Debug module");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -229,7 +229,7 @@ static void __exit cpuid_exit(void)
|
|||
for_each_online_cpu(cpu)
|
||||
cpuid_device_destroy(cpu);
|
||||
class_destroy(cpuid_class);
|
||||
unregister_chrdev(CPUID_MAJOR, "cpu/cpuid");
|
||||
__unregister_chrdev(CPUID_MAJOR, 0, NR_CPUS, "cpu/cpuid");
|
||||
unregister_hotcpu_notifier(&cpuid_class_cpu_notifier);
|
||||
}
|
||||
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
*/
|
||||
unsigned long hpet_address;
|
||||
u8 hpet_blockid; /* OS timer block num */
|
||||
u8 hpet_msi_disable;
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
static unsigned long hpet_num_timers;
|
||||
#endif
|
||||
|
@ -596,6 +598,9 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
|
|||
unsigned int num_timers_used = 0;
|
||||
int i;
|
||||
|
||||
if (hpet_msi_disable)
|
||||
return;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_ARAT))
|
||||
return;
|
||||
id = hpet_readl(HPET_ID);
|
||||
|
@ -928,6 +933,9 @@ static __init int hpet_late_init(void)
|
|||
hpet_reserve_platform_timers(hpet_readl(HPET_ID));
|
||||
hpet_print_config();
|
||||
|
||||
if (hpet_msi_disable)
|
||||
return 0;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_ARAT))
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -36,9 +36,6 @@ MODULE_LICENSE("GPL v2");
|
|||
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
|
||||
#define UCODE_UCODE_TYPE 0x00000001
|
||||
|
||||
const struct firmware *firmware;
|
||||
static int supported_cpu;
|
||||
|
||||
struct equiv_cpu_entry {
|
||||
u32 installed_cpu;
|
||||
u32 fixed_errata_mask;
|
||||
|
@ -77,12 +74,15 @@ static struct equiv_cpu_entry *equiv_cpu_table;
|
|||
|
||||
static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||
u32 dummy;
|
||||
|
||||
if (!supported_cpu)
|
||||
return -1;
|
||||
|
||||
memset(csig, 0, sizeof(*csig));
|
||||
if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
|
||||
pr_warning("microcode: CPU%d: AMD CPU family 0x%x not "
|
||||
"supported\n", cpu, c->x86);
|
||||
return -1;
|
||||
}
|
||||
rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
|
||||
pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev);
|
||||
return 0;
|
||||
|
@ -294,10 +294,14 @@ generic_load_microcode(int cpu, const u8 *data, size_t size)
|
|||
|
||||
static enum ucode_state request_microcode_fw(int cpu, struct device *device)
|
||||
{
|
||||
const char *fw_name = "amd-ucode/microcode_amd.bin";
|
||||
const struct firmware *firmware;
|
||||
enum ucode_state ret;
|
||||
|
||||
if (firmware == NULL)
|
||||
if (request_firmware(&firmware, fw_name, device)) {
|
||||
printk(KERN_ERR "microcode: failed to load file %s\n", fw_name);
|
||||
return UCODE_NFOUND;
|
||||
}
|
||||
|
||||
if (*(u32 *)firmware->data != UCODE_MAGIC) {
|
||||
pr_err("invalid UCODE_MAGIC (0x%08x)\n",
|
||||
|
@ -307,6 +311,8 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device)
|
|||
|
||||
ret = generic_load_microcode(cpu, firmware->data, firmware->size);
|
||||
|
||||
release_firmware(firmware);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -325,31 +331,7 @@ static void microcode_fini_cpu_amd(int cpu)
|
|||
uci->mc = NULL;
|
||||
}
|
||||
|
||||
void init_microcode_amd(struct device *device)
|
||||
{
|
||||
const char *fw_name = "amd-ucode/microcode_amd.bin";
|
||||
struct cpuinfo_x86 *c = &boot_cpu_data;
|
||||
|
||||
WARN_ON(c->x86_vendor != X86_VENDOR_AMD);
|
||||
|
||||
if (c->x86 < 0x10) {
|
||||
pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
|
||||
return;
|
||||
}
|
||||
supported_cpu = 1;
|
||||
|
||||
if (request_firmware(&firmware, fw_name, device))
|
||||
pr_err("failed to load file %s\n", fw_name);
|
||||
}
|
||||
|
||||
void fini_microcode_amd(void)
|
||||
{
|
||||
release_firmware(firmware);
|
||||
}
|
||||
|
||||
static struct microcode_ops microcode_amd_ops = {
|
||||
.init = init_microcode_amd,
|
||||
.fini = fini_microcode_amd,
|
||||
.request_microcode_user = request_microcode_user,
|
||||
.request_microcode_fw = request_microcode_fw,
|
||||
.collect_cpu_info = collect_cpu_info_amd,
|
||||
|
|
|
@ -521,9 +521,6 @@ static int __init microcode_init(void)
|
|||
return PTR_ERR(microcode_pdev);
|
||||
}
|
||||
|
||||
if (microcode_ops->init)
|
||||
microcode_ops->init(µcode_pdev->dev);
|
||||
|
||||
get_online_cpus();
|
||||
mutex_lock(µcode_mutex);
|
||||
|
||||
|
@ -566,9 +563,6 @@ static void __exit microcode_exit(void)
|
|||
|
||||
platform_device_unregister(microcode_pdev);
|
||||
|
||||
if (microcode_ops->fini)
|
||||
microcode_ops->fini();
|
||||
|
||||
microcode_ops = NULL;
|
||||
|
||||
pr_info("Microcode Update Driver: v" MICROCODE_VERSION " removed.\n");
|
||||
|
|
|
@ -285,7 +285,7 @@ static void __exit msr_exit(void)
|
|||
for_each_online_cpu(cpu)
|
||||
msr_device_destroy(cpu);
|
||||
class_destroy(msr_class);
|
||||
unregister_chrdev(MSR_MAJOR, "cpu/msr");
|
||||
__unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
|
||||
unregister_hotcpu_notifier(&msr_class_cpu_notifier);
|
||||
}
|
||||
|
||||
|
|
|
@ -491,6 +491,19 @@ void force_hpet_resume(void)
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* HPET MSI on some boards (ATI SB700/SB800) has side effect on
|
||||
* floppy DMA. Disable HPET MSI on such platforms.
|
||||
*/
|
||||
static void force_disable_hpet_msi(struct pci_dev *unused)
|
||||
{
|
||||
hpet_msi_disable = 1;
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
|
||||
force_disable_hpet_msi);
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
|
||||
|
|
|
@ -229,9 +229,11 @@ update_nodes_add(int node, unsigned long start, unsigned long end)
|
|||
printk(KERN_ERR "SRAT: Hotplug zone not continuous. Partly ignored\n");
|
||||
}
|
||||
|
||||
if (changed)
|
||||
if (changed) {
|
||||
node_set(node, cpu_nodes_parsed);
|
||||
printk(KERN_INFO "SRAT: hot plug zone found %Lx - %Lx\n",
|
||||
nd->start, nd->end);
|
||||
}
|
||||
}
|
||||
|
||||
/* Callback for parsing of the Proximity Domain <-> Memory Area mappings */
|
||||
|
|
Reference in a new issue