From c7c6b39050aed4af913c17970ebfb592bae757fc Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 27 Nov 2007 19:31:33 +0100 Subject: [PATCH] [MIPS] Use correct dma flushing in dma_cache_sync() Not cache coherent R10k systems (like IP28) need to do real cache invalidates in dma_cache_sync(). Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/mm/dma-default.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 810535dd091..ae39dd88b9a 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, BUG_ON(direction == DMA_NONE); if (!plat_device_is_coherent(dev)) - dma_cache_wback_inv((unsigned long)vaddr, size); + __dma_sync((unsigned long)vaddr, size, direction); } EXPORT_SYMBOL(dma_cache_sync);