[ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
The current S3C24XX DMA code does not allow for an peripheral that has one channel for RX and another for TX. This patch adds a per-cpu dma operation to select the transmit or receive channel, and adds support to the S3C2412 for the seperate DMA channels for TX and RX. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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67d729adc0
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c6709e8ef5
3 changed files with 54 additions and 6 deletions
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@ -40,106 +40,141 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
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[DMACH_XD0] = {
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.name = "xdreq0",
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.channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
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.channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ0),
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},
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[DMACH_XD1] = {
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.name = "xdreq1",
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.channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
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.channels_rx = MAP(S3C2412_DMAREQSEL_XDREQ1),
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},
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[DMACH_SDI] = {
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.name = "sdi",
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.channels = MAP(S3C2412_DMAREQSEL_SDI),
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.channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
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.hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
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.hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
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},
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[DMACH_SPI0] = {
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.name = "spi0",
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.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
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.channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
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.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
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},
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[DMACH_SPI1] = {
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.name = "spi1",
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.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
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.channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
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.hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
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},
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[DMACH_UART0] = {
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.name = "uart0",
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.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
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.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
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},
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[DMACH_UART1] = {
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.name = "uart1",
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.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
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.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
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},
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[DMACH_UART2] = {
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.name = "uart2",
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.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
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.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
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},
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[DMACH_UART0_SRC2] = {
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.name = "uart0",
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.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
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.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
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},
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[DMACH_UART1_SRC2] = {
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.name = "uart1",
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.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
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.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
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},
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[DMACH_UART2_SRC2] = {
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.name = "uart2",
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.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
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.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
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.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
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},
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[DMACH_TIMER] = {
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.name = "timer",
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.channels = MAP(S3C2412_DMAREQSEL_TIMER),
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.channels_rx = MAP(S3C2412_DMAREQSEL_TIMER),
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},
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[DMACH_I2S_IN] = {
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.name = "i2s-sdi",
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.channels = MAP(S3C2412_DMAREQSEL_I2SRX),
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.channels_rx = MAP(S3C2412_DMAREQSEL_I2SRX),
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.hw_addr.from = S3C2410_PA_IIS + S3C2412_IISRXD,
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},
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[DMACH_I2S_OUT] = {
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.name = "i2s-sdo",
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.channels = MAP(S3C2412_DMAREQSEL_I2STX),
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.channels_rx = MAP(S3C2412_DMAREQSEL_I2STX),
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.hw_addr.to = S3C2410_PA_IIS + S3C2412_IISTXD,
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},
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[DMACH_USB_EP1] = {
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.name = "usb-ep1",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP1),
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.channels_rx = MAP(S3C2412_DMAREQSEL_USBEP1),
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},
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[DMACH_USB_EP2] = {
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.name = "usb-ep2",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP2),
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.channels_rx = MAP(S3C2412_DMAREQSEL_USBEP2),
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},
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[DMACH_USB_EP3] = {
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.name = "usb-ep3",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP3),
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.channels_rx = MAP(S3C2412_DMAREQSEL_USBEP3),
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},
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[DMACH_USB_EP4] = {
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.name = "usb-ep4",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP4),
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.channels_rx = MAP(S3C2412_DMAREQSEL_USBEP4),
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},
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};
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static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map,
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enum s3c2410_dmasrc dir)
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{
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unsigned long chsel;
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if (dir == S3C2410_DMASRC_HW)
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chsel = map->channels_rx[0];
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else
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chsel = map->channels[0];
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chsel &= ~DMA_CH_VALID;
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chsel |= S3C2412_DMAREQSEL_HW;
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writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
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}
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static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map)
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{
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writel(map->channels[0] | S3C2412_DMAREQSEL_HW,
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chan->regs + S3C2412_DMA_DMAREQSEL);
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s3c2412_dma_direction(chan, map, chan->source);
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}
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static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
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.select = s3c2412_dma_select,
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.direction = s3c2412_dma_direction,
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.dcon_mask = 0,
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.map = s3c2412_dma_mappings,
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.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
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@ -1184,7 +1184,7 @@ int s3c2410_dma_devconfig(int channel,
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dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
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chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
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return 0;
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break;
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case S3C2410_DMASRC_MEM:
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/* source is memory */
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@ -1195,11 +1195,19 @@ int s3c2410_dma_devconfig(int channel,
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dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
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chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
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return 0;
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break;
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default:
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printk(KERN_ERR "dma%d: invalid source type (%d)\n",
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channel, source);
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return -EINVAL;
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}
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printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
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return -EINVAL;
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if (dma_sel.direction != NULL)
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(dma_sel.direction)(chan, chan->map, source);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_dma_devconfig);
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@ -32,6 +32,7 @@ struct s3c24xx_dma_map {
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struct s3c24xx_dma_addr hw_addr;
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unsigned long channels[S3C2410_DMA_CHANNELS];
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unsigned long channels_rx[S3C2410_DMA_CHANNELS];
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};
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struct s3c24xx_dma_selection {
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@ -41,6 +42,10 @@ struct s3c24xx_dma_selection {
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void (*select)(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map);
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void (*direction)(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map,
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enum s3c2410_dmasrc dir);
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};
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extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
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