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powerpc: Remove use of a second scratch SPRG in STAB code 

The STAB code used on Power3 and RS/64 uses a second scratch SPRG to
save a GPR in order to decide whether to go to do_stab_bolted_* or
to handle a normal data access exception.

This prevents our scheme of freeing SPRG3 which is user visible for
user uses since we cannot use SPRG0 which, on RS/64, seems to be
read-only for supervisor mode (like POWER4).

This reworks the STAB exception entry to use the PACA as temporary
storage instead.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2009-07-16 19:36:57 +00:00
parent ee43eb788b
commit c5a8c0c99f
4 changed files with 55 additions and 30 deletions
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7
arch/powerpc/include/asm/exception-64s.h
View File

@ -66,8 +66,7 @@
std r9,area+EX_R13(r13); \
mfcr r9
#define EXCEPTION_PROLOG_PSERIES(area, label) \
EXCEPTION_PROLOG_1(area); \
#define EXCEPTION_PROLOG_PSERIES_1(label) \
ld r12,PACAKBASE(r13); /* get high part of &label */ \
ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
mfspr r11,SPRN_SRR0; /* save SRR0 */ \
@ -78,6 +77,10 @@
rfid; \
b . /* prevent speculative execution */
#define EXCEPTION_PROLOG_PSERIES(area, label) \
EXCEPTION_PROLOG_1(area); \
EXCEPTION_PROLOG_PSERIES_1(label);
/*
* The common exception prolog is used for all except a few exceptions
* such as a segment miss on a kernel address. We have to be prepared

3
arch/powerpc/include/asm/reg.h
View File

@ -654,7 +654,7 @@
* 64-bit server:
* - SPRG0 unused (reserved for HV on Power4)
* - SPRG1 scratch for exception vectors
* - SPRG2 scratch for exception vectors
* - SPRG2 unused
*
* All 32-bit:
* - SPRG3 current thread_info pointer
@ -707,7 +707,6 @@
#ifdef CONFIG_PPC_BOOK3S_64
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG1
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG2
#endif
#ifdef CONFIG_PPC_BOOK3S_32

38
arch/powerpc/kernel/exceptions-64s.S
View File

@ -50,18 +50,28 @@ data_access_pSeries:
HMT_MEDIUM
mtspr SPRN_SPRG_SCRATCH0,r13
BEGIN_FTR_SECTION
mtspr SPRN_SPRG_SCRATCH1,r12
mfspr r13,SPRN_DAR
mfspr r12,SPRN_DSISR
srdi r13,r13,60
rlwimi r13,r12,16,0x20
mfcr r12
cmpwi r13,0x2c
mfspr r13,SPRN_SPRG_PACA
std r9,PACA_EXSLB+EX_R9(r13)
std r10,PACA_EXSLB+EX_R10(r13)
mfspr r10,SPRN_DAR
mfspr r9,SPRN_DSISR
srdi r10,r10,60
rlwimi r10,r9,16,0x20
mfcr r9
cmpwi r10,0x2c
beq do_stab_bolted_pSeries
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG_SCRATCH1
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
ld r10,PACA_EXSLB+EX_R10(r13)
std r11,PACA_EXGEN+EX_R11(r13)
ld r11,PACA_EXSLB+EX_R9(r13)
std r12,PACA_EXGEN+EX_R12(r13)
mfspr r12,SPRN_SPRG_SCRATCH0
std r10,PACA_EXGEN+EX_R10(r13)
std r11,PACA_EXGEN+EX_R9(r13)
std r12,PACA_EXGEN+EX_R13(r13)
EXCEPTION_PROLOG_PSERIES_1(data_access_common)
FTR_SECTION_ELSE
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
. = 0x380
.globl data_access_slb_pSeries
@ -224,9 +234,11 @@ masked_interrupt:
.align 7
do_stab_bolted_pSeries:
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG_SCRATCH1
EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
std r11,PACA_EXSLB+EX_R11(r13)
std r12,PACA_EXSLB+EX_R12(r13)
mfspr r10,SPRN_SPRG_SCRATCH0
std r10,PACA_EXSLB+EX_R13(r13)
EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted)
#ifdef CONFIG_PPC_PSERIES
/*

37
arch/powerpc/platforms/iseries/exception.S
View File

@ -128,25 +128,36 @@ iSeries_secondary_smp_loop:
data_access_iSeries:
mtspr SPRN_SPRG_SCRATCH0,r13
BEGIN_FTR_SECTION
mtspr SPRN_SPRG_SCRATCH1,r12
mfspr r13,SPRN_DAR
mfspr r12,SPRN_DSISR
srdi r13,r13,60
rlwimi r13,r12,16,0x20
mfcr r12
cmpwi r13,0x2c
mfspr r13,SPRN_SPRG_PACA
std r9,PACA_EXSLB+EX_R9(r13)
std r10,PACA_EXSLB+EX_R10(r13)
mfspr r10,SPRN_DAR
mfspr r9,SPRN_DSISR
srdi r10,r10,60
rlwimi r10,r9,16,0x20
mfcr r9
cmpwi r10,0x2c
beq .do_stab_bolted_iSeries
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG_SCRATCH1
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
ld r10,PACA_EXSLB+EX_R10(r13)
std r11,PACA_EXGEN+EX_R11(r13)
ld r11,PACA_EXSLB+EX_R9(r13)
std r12,PACA_EXGEN+EX_R12(r13)
mfspr r12,SPRN_SPRG_SCRATCH0
std r10,PACA_EXGEN+EX_R10(r13)
std r11,PACA_EXGEN+EX_R9(r13)
std r12,PACA_EXGEN+EX_R13(r13)
EXCEPTION_PROLOG_ISERIES_1
FTR_SECTION_ELSE
EXCEPTION_PROLOG_1(PACA_EXGEN)
EXCEPTION_PROLOG_ISERIES_1
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
b data_access_common
.do_stab_bolted_iSeries:
mtcrf 0x80,r12
mfspr r12,SPRN_SPRG_SCRATCH1
EXCEPTION_PROLOG_1(PACA_EXSLB)
std r11,PACA_EXSLB+EX_R11(r13)
std r12,PACA_EXSLB+EX_R12(r13)
mfspr r10,SPRN_SPRG_SCRATCH0
std r10,PACA_EXSLB+EX_R13(r13)
EXCEPTION_PROLOG_ISERIES_1
b .do_stab_bolted