OMAPDSS: DISPC: Use a common function to set manager timings
Currently, a LCD manager's timings is set by dispc_mgr_set_lcd_timings() and TV manager's timings is set by dispc_set_digit_size(). Use a common function called dispc_mgr_set_timings() which sets timings for both type of managers. We finally want the interface drivers to use an overlay manager function to configure it's timings, having a common DISPC function would make things cleaner. For LCD managers, dispc_mgr_set_timings() sets LCD size and blanking values, for TV manager, it sets only the TV size since blanking values don't exist for TV. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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8 changed files with 40 additions and 34 deletions
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@ -992,7 +992,7 @@ static void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width,
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dispc_write_reg(DISPC_SIZE_MGR(channel), val);
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dispc_write_reg(DISPC_SIZE_MGR(channel), val);
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}
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}
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void dispc_set_digit_size(u16 width, u16 height)
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static void dispc_mgr_set_digit_size(u16 width, u16 height)
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{
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{
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u32 val;
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u32 val;
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BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
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BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
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@ -2341,37 +2341,42 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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}
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}
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/* change name to mode? */
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/* change name to mode? */
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void dispc_mgr_set_lcd_timings(enum omap_channel channel,
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void dispc_mgr_set_timings(enum omap_channel channel,
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struct omap_video_timings *timings)
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struct omap_video_timings *timings)
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{
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{
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unsigned xtot, ytot;
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unsigned xtot, ytot;
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unsigned long ht, vt;
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unsigned long ht, vt;
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if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
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timings->hbp, timings->vsw,
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timings->vfp, timings->vbp))
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BUG();
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_dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
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timings->hbp, timings->vsw, timings->vfp,
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timings->vbp);
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dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
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xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
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ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
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ht = (timings->pixel_clock * 1000) / xtot;
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vt = (timings->pixel_clock * 1000) / xtot / ytot;
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DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
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DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
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timings->y_res);
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timings->y_res);
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DSSDBG("pck %u\n", timings->pixel_clock);
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DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
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if (dispc_mgr_is_lcd(channel)) {
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if (!dispc_lcd_timings_ok(timings))
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BUG();
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_dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
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timings->hbp, timings->vsw, timings->vfp,
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timings->vbp);
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dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
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xtot = timings->x_res + timings->hfp + timings->hsw +
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timings->hbp;
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ytot = timings->y_res + timings->vfp + timings->vsw +
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timings->vbp;
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ht = (timings->pixel_clock * 1000) / xtot;
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vt = (timings->pixel_clock * 1000) / xtot / ytot;
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DSSDBG("pck %u\n", timings->pixel_clock);
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DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
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timings->hsw, timings->hfp, timings->hbp,
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timings->hsw, timings->hfp, timings->hbp,
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timings->vsw, timings->vfp, timings->vbp);
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timings->vsw, timings->vfp, timings->vbp);
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DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
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DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
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} else {
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dispc_mgr_set_digit_size(timings->x_res, timings->y_res);
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}
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}
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}
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static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
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static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
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@ -156,7 +156,7 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
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t->pixel_clock = pck;
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t->pixel_clock = pck;
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}
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}
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dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
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dispc_mgr_set_timings(dssdev->manager->id, t);
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return 0;
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return 0;
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}
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}
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@ -4219,12 +4219,12 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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dispc_mgr_enable_stallmode(dssdev->manager->id, true);
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dispc_mgr_enable_stallmode(dssdev->manager->id, true);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
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dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
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dispc_mgr_set_timings(dssdev->manager->id, &timings);
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} else {
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} else {
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dispc_mgr_enable_stallmode(dssdev->manager->id, false);
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dispc_mgr_enable_stallmode(dssdev->manager->id, false);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
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dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
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dispc_mgr_set_lcd_timings(dssdev->manager->id,
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dispc_mgr_set_timings(dssdev->manager->id,
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&dssdev->panel.timings);
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&dssdev->panel.timings);
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}
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}
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@ -407,7 +407,6 @@ void dispc_disable_sidle(void);
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void dispc_lcd_enable_signal_polarity(bool act_high);
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void dispc_lcd_enable_signal_polarity(bool act_high);
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void dispc_lcd_enable_signal(bool enable);
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void dispc_lcd_enable_signal(bool enable);
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void dispc_pck_free_enable(bool enable);
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void dispc_pck_free_enable(bool enable);
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void dispc_set_digit_size(u16 width, u16 height);
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void dispc_enable_fifomerge(bool enable);
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void dispc_enable_fifomerge(bool enable);
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void dispc_enable_gamma_table(bool enable);
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void dispc_enable_gamma_table(bool enable);
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void dispc_set_loadmode(enum omap_dss_load_mode mode);
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void dispc_set_loadmode(enum omap_dss_load_mode mode);
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@ -442,7 +441,7 @@ void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
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void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
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void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
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void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
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void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
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enum omap_lcd_display_type type);
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enum omap_lcd_display_type type);
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void dispc_mgr_set_lcd_timings(enum omap_channel channel,
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void dispc_mgr_set_timings(enum omap_channel channel,
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struct omap_video_timings *timings);
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struct omap_video_timings *timings);
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void dispc_mgr_set_pol_freq(enum omap_channel channel,
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void dispc_mgr_set_pol_freq(enum omap_channel channel,
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enum omap_panel_config config, u8 acbi, u8 acb);
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enum omap_panel_config config, u8 acbi, u8 acb);
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@ -376,8 +376,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
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dispc_enable_gamma_table(0);
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dispc_enable_gamma_table(0);
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/* tv size */
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/* tv size */
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dispc_set_digit_size(dssdev->panel.timings.x_res,
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dispc_mgr_set_timings(dssdev->manager->id, &dssdev->panel.timings);
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dssdev->panel.timings.y_res);
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hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
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hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
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@ -320,7 +320,7 @@ static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
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DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
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DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
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dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
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dispc_mgr_set_timings(dssdev->manager->id, &timings);
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dispc_mgr_enable(dssdev->manager->id, true);
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dispc_mgr_enable(dssdev->manager->id, true);
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@ -804,7 +804,7 @@ int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
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if (*w == 0 || *h == 0)
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if (*w == 0 || *h == 0)
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return -EINVAL;
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return -EINVAL;
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dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
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dispc_mgr_set_timings(dssdev->manager->id, &timings);
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return 0;
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return 0;
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}
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}
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@ -107,7 +107,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
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}
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}
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dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
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dispc_mgr_set_timings(dssdev->manager->id, t);
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r = dss_set_clock_div(&dss_cinfo);
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r = dss_set_clock_div(&dss_cinfo);
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if (r)
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if (r)
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@ -421,6 +421,7 @@ static int venc_power_on(struct omap_dss_device *dssdev)
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{
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{
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u32 l;
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u32 l;
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int r;
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int r;
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struct omap_video_timings timings;
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venc_reset();
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venc_reset();
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venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
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venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
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@ -440,8 +441,10 @@ static int venc_power_on(struct omap_dss_device *dssdev)
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venc_write_reg(VENC_OUTPUT_CONTROL, l);
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venc_write_reg(VENC_OUTPUT_CONTROL, l);
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dispc_set_digit_size(dssdev->panel.timings.x_res,
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timings = dssdev->panel.timings;
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dssdev->panel.timings.y_res/2);
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timings.y_res /= 2;
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dispc_mgr_set_timings(dssdev->manager->id, &timings);
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r = regulator_enable(venc.vdda_dac_reg);
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r = regulator_enable(venc.vdda_dac_reg);
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if (r)
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if (r)
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