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ARM: EXYNOS: DT Support for SATA and SATA PHY 

This patch adds Device Nodes for SATA and SATA PHY device.

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
[kgene.kim@samsung.com: removed address definitions as per comments]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Vasanth Ananthan 2012-11-20 21:02:11 +09:00 committed by Kukjin Kim
parent d36bb0f040
commit c47d244a64
5 changed files with 70 additions and 0 deletions
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14
Documentation/devicetree/bindings/ata/exynos-sata-phy.txt Normal file
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@ -0,0 +1,14 @@
* Samsung SATA PHY Controller
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata-phy"
- reg : <registers mapping>
Example:
sata@ffe07000 {
compatible = "samsung,exynos5-sata-phy";
reg = <0xffe07000 0x1000>;
};

17
Documentation/devicetree/bindings/ata/exynos-sata.txt Normal file
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@ -0,0 +1,17 @@
* Samsung AHCI SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
Example:
sata@ffe08000 {
compatible = "samsung,exynos5-sata";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};

15
arch/arm/boot/dts/exynos5250-smdk5250.dts
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@ -55,6 +55,21 @@
};
};
i2c@121D0000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
samsung,i2c-slave-addr = <0x38>;
sata-phy {
compatible = "samsung,sata-phy";
reg = <0x38>;
};
};
sata@122F0000 {
samsung,sata-freq = <66>;
};
i2c@12C80000 {
status = "disabled";
};

18
arch/arm/boot/dts/exynos5250.dtsi
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@ -104,6 +104,17 @@
interrupts = <0 54 0>;
};
sata@122F0000 {
compatible = "samsung,exynos5-sata-ahci";
reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>;
};
sata-phy@12170000 {
compatible = "samsung,exynos5-sata-phy";
reg = <0x12170000 0x1ff>;
};
i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
@ -168,6 +179,13 @@
#size-cells = <0>;
};
i2c@121D0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x121D0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;

6
arch/arm/mach-exynos/mach-exynos5-dt.c
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@ -64,6 +64,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"exynos4210-spi.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
"exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
"exynos5-sata", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
"exynos5-sata-phy", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
"exynos5-sata-phy-i2c", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),