mmc: SDHC 3.0: Base clock frequency change in spec 3.0
SDHC Spec 3.0: Capabilities Register bits[15-08] are Base Clock Frequency 1.0/2.0: Capabilities Register bits[13-08] are Base Clock Frequency Signed-off-by: Zhangfei Gao <zgao6@marvell.com> Cc: David Vrabel <david.vrabel@csr.com> Cc: Matt Fleming <matt@console-pimps.org> Cc: Michal Miroslaw <mirqus@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Chris Ball <cjb@laptop.org>
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2 changed files with 8 additions and 2 deletions
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@ -1794,8 +1794,13 @@ int sdhci_add_host(struct sdhci_host *host)
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mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
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}
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host->max_clk =
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(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
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if (host->version >= SDHCI_SPEC_300)
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host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
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>> SDHCI_CLOCK_BASE_SHIFT;
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else
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host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
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>> SDHCI_CLOCK_BASE_SHIFT;
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host->max_clk *= 1000000;
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if (host->max_clk == 0 || host->quirks &
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
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@ -144,6 +144,7 @@
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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