staging: brcm80211: Remove siutils dependence from dhd_sdio.c
Remove siutils related functions and resources from dhd_sdio.c Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Franky Lin
Greg Kroah-Hartman
parent
cee3cf4bc3
commit
c05df63648
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@ -30,5 +30,6 @@
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#define BCM4329_CORE_SOCRAM_BASE 0x18003000
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/* ARM Cortex M3 core, ID 0x82a */
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#define BCM4329_CORE_ARM_BASE 0x18002000
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#define BCM4329_RAMSIZE 0x48000
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#endif /* _bcmchip_h_ */
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@ -180,6 +180,7 @@ struct chip_info {
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u32 ramcorebase;
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u32 armcorebase;
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u32 pmurev;
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u32 ramsize;
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};
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/* Private data for SDIO bus interaction */
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@ -187,7 +188,6 @@ typedef struct dhd_bus {
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dhd_pub_t *dhd;
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bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
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si_t *sih; /* Handle for SI calls */
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struct chip_info *ci; /* Chip info struct */
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char *vars; /* Variables (from CIS and/or other) */
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uint varsz; /* Size of variables buffer */
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@ -535,8 +535,8 @@ static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
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clkreq =
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bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
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if ((bus->sih->chip == BCM4329_CHIP_ID)
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&& (bus->sih->chiprev == 0))
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if ((bus->ci->chip == BCM4329_CHIP_ID)
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&& (bus->ci->chiprev == 0))
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clkreq |= SBSDIO_FORCE_ALP;
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bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
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@ -547,8 +547,8 @@ static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
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return BCME_ERROR;
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}
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if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
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&& (bus->sih->buscorerev == 9))) {
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if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
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&& (bus->ci->buscorerev == 9))) {
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u32 dummy, retries;
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R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
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}
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@ -842,8 +842,8 @@ int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
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SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
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/* Isolate the bus */
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if (bus->sih->chip != BCM4329_CHIP_ID
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&& bus->sih->chip != BCM4319_CHIP_ID) {
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if (bus->ci->chip != BCM4329_CHIP_ID
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&& bus->ci->chip != BCM4319_CHIP_ID) {
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bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
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SBSDIO_DEVCTL_PADS_ISO, NULL);
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}
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@ -859,8 +859,8 @@ int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
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/* Force pad isolation off if possible
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(in case power never toggled) */
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if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
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&& (bus->sih->buscorerev >= 10))
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if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
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&& (bus->ci->buscorerev >= 10))
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bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
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NULL);
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@ -2920,14 +2920,11 @@ int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
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/* If F2 successfully enabled, set core and enable interrupts */
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if (ready == enable) {
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/* Make sure we're talking to the core. */
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bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
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if (!(bus->regs))
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bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
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/* Set up the interrupt mask and enable interrupts */
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bus->hostintmask = HOSTINTMASK;
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W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
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W_SDREG(bus->hostintmask,
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(unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
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hostintmask), retries);
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bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
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(u8) watermark, &err);
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@ -5187,7 +5184,10 @@ dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
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#endif /* DHD_DEBUG */
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/* Force PLL off until si_attach() programs PLL control regs */
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/*
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* Force PLL off until dhdsdio_chip_attach()
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* programs PLL control regs
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*/
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bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
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DHD_INIT_CLKCTL1, &err);
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@ -5253,23 +5253,16 @@ dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
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}
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#endif /* DHD_DEBUG */
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/* si_attach() will provide an SI handle and scan the backplane */
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bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
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&bus->vars, &bus->varsz);
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if (!(bus->sih)) {
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DHD_ERROR(("%s: si_attach failed!\n", __func__));
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goto fail;
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}
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if (dhdsdio_chip_attach(bus, regsva)) {
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DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
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goto fail;
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}
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bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
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bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
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if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
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if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
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DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
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__func__, bus->sih->chip));
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__func__, bus->ci->chip));
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goto fail;
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}
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@ -5277,14 +5270,9 @@ dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
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/* Get info on the ARM and SOCRAM cores... */
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if (!DHD_NOPMU(bus)) {
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if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
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(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
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bus->armrev = si_corerev(bus->sih);
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} else {
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DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
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goto fail;
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}
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bus->orig_ramsize = si_socram_size(bus->sih);
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bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
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CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
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bus->orig_ramsize = bus->ci->ramsize;
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if (!(bus->orig_ramsize)) {
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DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
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__func__));
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@ -5298,17 +5286,7 @@ dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
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bus->ramsize, bus->orig_ramsize));
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}
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/* ...but normally deal with the SDPCMDEV core */
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bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
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if (!bus->regs) {
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bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
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if (!bus->regs) {
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DHD_ERROR(("%s: failed to find SDIODEV core!\n",
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__func__));
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goto fail;
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}
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}
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bus->sdpcmrev = si_corerev(bus->sih);
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bus->regs = (void *)bus->ci->buscorebase;
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/* Set core control so an SDIO reset does a backplane reset */
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OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
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@ -5522,13 +5500,9 @@ static void dhdsdio_release_dongle(dhd_bus_t *bus)
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if (bus->dhd && bus->dhd->dongle_reset)
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return;
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if (bus->sih) {
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if (bus->ci) {
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dhdsdio_clkctl(bus, CLK_AVAIL, false);
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#if !defined(BCMLXSDMMC)
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si_watchdog(bus->sih, 4);
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#endif /* !defined(BCMLXSDMMC) */
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dhdsdio_clkctl(bus, CLK_NONE, false);
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si_detach(bus->sih);
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dhdsdio_chip_detach(bus);
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if (bus->vars && bus->varsz)
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kfree(bus->vars);
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@ -5955,8 +5929,8 @@ dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
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uint dhd_bus_chip(struct dhd_bus *bus)
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{
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ASSERT(bus->sih != NULL);
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return bus->sih->chip;
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ASSERT(bus->ci != NULL);
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return bus->ci->chip;
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}
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void *dhd_bus_pub(struct dhd_bus *bus)
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@ -6071,6 +6045,7 @@ dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
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ci->buscorebase = BCM4329_CORE_BUS_BASE;
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ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
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ci->armcorebase = BCM4329_CORE_ARM_BASE;
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ci->ramsize = BCM4329_RAMSIZE;
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break;
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default:
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DHD_ERROR(("%s: chipid 0x%x is not supported\n",
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