ARM: S5PV310: Update CPUFREQ
This patch updates following of CPUFREQ. - Updated DVFS table and divider value - Added common function - Added some function for changing APLL and setting Signed-off-by: Sangwook Ju <sw.ju@samsung.com> Reviewed-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Sangwook Ju
Kukjin Kim
parent
f40f91fefc
commit
bf5ce054f5
1 changed files with 163 additions and 144 deletions
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@ -24,6 +24,7 @@
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#include <mach/regs-mem.h>
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#include <plat/clock.h>
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#include <plat/pm.h>
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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@ -36,7 +37,6 @@ static struct regulator *int_regulator;
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#endif
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static struct cpufreq_freqs freqs;
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static unsigned int armclk_use_apll;
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static unsigned int memtype;
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enum s5pv310_memory_type {
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@ -46,19 +46,18 @@ enum s5pv310_memory_type {
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};
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
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L0, L1, L2, L3, CPUFREQ_LEVEL_END,
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};
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static struct cpufreq_frequency_table s5pv310_freq_table[] = {
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{L0, 1000*1000},
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{L1, 800*1000},
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{L2, 400*1000},
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{L3, 200*1000},
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{L4, 100*1000},
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{L3, 100*1000},
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{0, CPUFREQ_TABLE_END},
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};
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = {
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static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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@ -66,25 +65,38 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END + 1][7] = {
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*/
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/* ARM L0: 1000MHz */
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{ 0, 3, 7, 3, 3, 0, 0 },
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L1: 800MHz */
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{ 0, 3, 7, 3, 3, 0, 0 },
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{ 0, 3, 7, 3, 3, 0, 1 },
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/* ARM L2: 400MHz */
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{ 1, 1, 3, 1, 1, 0, 0 },
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{ 0, 1, 3, 1, 3, 0, 1 },
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/* ARM L3: 200MHz */
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{ 3, 0, 1, 0, 0, 0, 0 },
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/* ARM L4A: 100MHz, for DDR2/3 */
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{ 7, 0, 1, 0, 0, 0, 0 },
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/* ARM L4B: 100MHz, for LPDDR2 (SMDKV310 has LPDDR2) */
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{ 7, 0, 1, 0, 0, 0, 0 },
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/* ARM L3: 100MHz */
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{ 0, 0, 1, 0, 3, 1, 1 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = {
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static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVCOPY, DIVHPM }
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*/
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/* ARM L0: 1000MHz */
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{ 3, 0 },
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/* ARM L1: 800MHz */
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{ 3, 0 },
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/* ARM L2: 400MHz */
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{ 3, 0 },
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/* ARM L3: 100MHz */
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{ 3, 0 },
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};
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static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
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@ -97,20 +109,14 @@ static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END + 1][8] = {
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/* DMC L1: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L2: 266.7MHz */
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{ 7, 1, 1, 2, 1, 1, 3, 1 },
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/* DMC L3: 400MHz */
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{ 3, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L4A: 400MHz, for DDR2/3 */
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{ 7, 1, 1, 1, 1, 1, 3, 1 },
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/* DMC L4B: 200MHz, for LPDDR2 */
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/* DMC L3: 200MHz */
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{ 7, 1, 1, 3, 1, 1, 3, 1 },
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};
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = {
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static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
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/*
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* Clock divider value for following
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* { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
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@ -122,20 +128,14 @@ static unsigned int clkdiv_top[CPUFREQ_LEVEL_END + 1][5] = {
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/* ACLK200 L1: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L2: 160MHz */
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{ 4, 7, 5, 7, 1 },
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/* ACLK200 L3: 200MHz */
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{ 3, 7, 4, 5, 1 },
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/* ACLK200 L4A: 100MHz */
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{ 7, 7, 7, 7, 1 },
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/* ACLK200 L4B: 100MHz */
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{ 7, 7, 7, 7, 1 },
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/* ACLK200 L3: 133.3MHz */
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{ 5, 7, 7, 7, 1 },
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};
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = {
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static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
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/*
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* Clock divider value for following
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* { DIVGDL/R, DIVGPL/R }
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@ -147,17 +147,11 @@ static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END + 1][2] = {
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/* ACLK_GDL/R L1: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L2: 160MHz */
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{ 4, 1 },
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/* ACLK_GDL/R L3: 200MHz */
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{ 3, 1 },
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/* ACLK_GDL/R L4A: 100MHz */
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{ 7, 1 },
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/* ACLK_GDL/R L4B: 100MHz */
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{ 7, 1 },
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/* ACLK_GDL/R L3: 133.3MHz */
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{ 5, 1 },
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};
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struct cpufreq_voltage_table {
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@ -166,7 +160,7 @@ struct cpufreq_voltage_table {
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unsigned int int_volt;
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};
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static struct cpufreq_voltage_table s5pv310_volt_table[] = {
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static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
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{
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.index = L0,
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.arm_volt = 1200000,
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@ -177,19 +171,29 @@ static struct cpufreq_voltage_table s5pv310_volt_table[] = {
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.int_volt = 1100000,
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}, {
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.index = L2,
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.arm_volt = 1050000,
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.int_volt = 1100000,
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}, {
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.index = L3,
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.arm_volt = 1050000,
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.int_volt = 1100000,
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}, {
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.index = L4,
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.arm_volt = 1000000,
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.int_volt = 1000000,
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}, {
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.index = L3,
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.arm_volt = 900000,
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.int_volt = 1000000,
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},
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};
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static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* APLL FOUT L0: 1000MHz */
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((250 << 16) | (6 << 8) | 1),
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/* APLL FOUT L1: 800MHz */
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((200 << 16) | (6 << 8) | 1),
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/* APLL FOUT L2 : 400MHz */
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((200 << 16) | (6 << 8) | 2),
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/* APLL FOUT L3: 100MHz */
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((200 << 16) | (6 << 8) | 4),
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};
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int s5pv310_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
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@ -227,6 +231,21 @@ void s5pv310_set_clkdiv(unsigned int div_index)
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tmp = __raw_readl(S5P_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = __raw_readl(S5P_CLKDIV_CPU1);
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tmp &= ~((0x7 << 4) | 0x7);
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tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
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(clkdiv_cpu1[div_index][1] << 0));
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__raw_writel(tmp, S5P_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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/* Change Divider - DMC0 */
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tmp = __raw_readl(S5P_CLKDIV_DMC0);
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@ -302,16 +321,100 @@ void s5pv310_set_clkdiv(unsigned int div_index)
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} while (tmp & 0x11);
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}
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static void s5pv310_set_apll(unsigned int index)
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{
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unsigned int tmp;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
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>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= s5pv310_apll_pms_table[index];
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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tmp = __raw_readl(S5P_APLL_CON0);
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} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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/* The frequency changing to L0 needs to change apll */
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if (freqs.new == s5pv310_freq_table[L0].frequency) {
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/* 1. Change the system clock divider values */
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s5pv310_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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s5pv310_set_apll(new_index);
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} else {
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/* 1. Change the system clock divider values */
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s5pv310_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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}
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}
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else if (old_index < new_index) {
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/* The frequency changing from L0 needs to change apll */
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if (freqs.old == s5pv310_freq_table[L0].frequency) {
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/* 1. Change the apll m,p,s value */
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s5pv310_set_apll(new_index);
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/* 2. Change the system clock divider values */
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s5pv310_set_clkdiv(new_index);
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} else {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 2. Change the system clock divider values */
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s5pv310_set_clkdiv(new_index);
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}
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}
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}
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static int s5pv310_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int index, div_index, tmp;
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unsigned int index, old_index;
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unsigned int arm_volt, int_volt;
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unsigned int need_apll = 0;
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freqs.old = s5pv310_getspeed(policy->cpu);
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if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
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freqs.old, relation, &old_index))
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return -EINVAL;
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if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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@ -322,19 +425,6 @@ static int s5pv310_target(struct cpufreq_policy *policy,
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if (freqs.new == freqs.old)
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return 0;
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/*
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* If freqs.new is higher than 800MHz
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* cpufreq driver should turn on apll
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*/
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if (index < L1)
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need_apll = 1;
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/* If the memory type is LPDDR2, use L4-B instead of L4-A */
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if ((index == L4) && (memtype == LPDDR2))
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div_index = index + 1;
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else
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div_index = index;
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/* get the voltage value */
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arm_volt = s5pv310_volt_table[index].arm_volt;
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int_volt = s5pv310_volt_table[index].int_volt;
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@ -351,69 +441,7 @@ static int s5pv310_target(struct cpufreq_policy *policy,
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}
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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s5pv310_set_clkdiv(div_index);
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/* 2. Change the divider values for special clocks in CMU_TOP */
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/* currently nothing */
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/* 3. Change the XPLL values or Select the parent XPLL */
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if (need_apll) {
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if (!armclk_use_apll) {
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/*
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* If the parent clock of armclk isn't apll
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* here need to set apll (include m,p,s value)
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*/
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/* a. MUX_CORE_SEL = MPLL,
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* ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
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>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* b. Set APLL Lock time */
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__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
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/* c. Change PLL PMS values */
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__raw_writel(S5P_APLL_VAL_1000, S5P_APLL_CON0);
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/* d. Turn on a PLL */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp |= (0x1 << S5P_APLLCON0_ENABLE_SHIFT);
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__raw_writel(tmp, S5P_APLL_CON0);
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/* e. wait_lock_time */
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do {
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tmp = __raw_readl(S5P_APLL_CON0);
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} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
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armclk_use_apll = 1;
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}
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/* MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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} else {
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if (clk_get_parent(moutcore) != mout_mpll) {
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = __raw_readl(S5P_CLKMUX_STATCPU);
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tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x2 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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}
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s5pv310_set_frequency(old_index, index);
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/* control regulator */
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if (freqs.new < freqs.old) {
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@ -477,8 +505,6 @@ static struct cpufreq_driver s5pv310_driver = {
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static int __init s5pv310_cpufreq_init(void)
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{
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unsigned int tmp;
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -509,13 +535,6 @@ static int __init s5pv310_cpufreq_init(void)
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}
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#endif
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/* check parent clock of armclk */
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tmp = __raw_readl(S5P_CLKSRC_CPU);
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||||
if (tmp & S5P_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
armclk_use_apll = 0;
|
||||
else
|
||||
armclk_use_apll = 1;
|
||||
|
||||
/*
|
||||
* Check DRAM type.
|
||||
* Because DVFS level is different according to DRAM type.
|
||||
|
|
|
|||
Reference in a new issue