Merge with ARM SMP tree
This commit is contained in:
Russell King
Russell King
commit
be6eb9b79f
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@ -358,7 +358,7 @@ config HOTPLUG_CPU
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config LOCAL_TIMERS
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bool "Use local timer interrupts"
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depends on SMP && n
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depends on SMP && REALVIEW_MPCORE
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default y
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help
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Enable support for local timers on SMP platforms, rather then the
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@ -5,3 +5,5 @@
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obj-y := core.o clock.o
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obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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@ -550,7 +550,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id, struct pt_reg
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timer_tick(regs);
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#ifdef CONFIG_SMP
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#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
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smp_send_timer();
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update_process_times(user_mode(regs));
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#endif
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@ -0,0 +1,138 @@
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/*
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* linux/arch/arm/mach-realview/hotplug.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <linux/completion.h>
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extern volatile int pen_release;
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static DECLARE_COMPLETION(cpu_killed);
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static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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asm volatile( "mcr p15, 0, %1, c7, c14, 0\n"
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, #0x04\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "r" (0)
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: "cc");
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}
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static inline void cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, #0x04\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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:
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: "cc");
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}
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static inline void platform_do_lowpower(unsigned int cpu)
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{
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/*
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* there is no power-control hardware on this platform, so all
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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for (;;) {
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/*
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* here's the WFI
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*/
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asm(".word 0xe320f003\n"
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:
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:
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: "memory", "cc");
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if (pen_release == cpu) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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/*
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* getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* The trouble is, letting people know about this is not really
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* possible, since we are currently running incoherently, and
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* therefore cannot safely call printk() or anything else
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*/
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#ifdef DEBUG
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printk("CPU%u: spurious wakeup call\n", cpu);
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#endif
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}
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}
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int platform_cpu_kill(unsigned int cpu)
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{
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return wait_for_completion_timeout(&cpu_killed, 5000);
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void platform_cpu_die(unsigned int cpu)
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{
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#ifdef DEBUG
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unsigned int this_cpu = hard_smp_processor_id();
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if (cpu != this_cpu) {
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printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
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this_cpu, cpu);
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BUG();
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}
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#endif
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printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
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complete(&cpu_killed);
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/*
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* we're ready for shutdown now, so do it
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*/
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cpu_enter_lowpower();
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platform_do_lowpower(cpu);
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/*
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* bring this CPU back into the world of cache
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* coherency, and then restore interrupts
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*/
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cpu_leave_lowpower();
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}
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int mach_cpu_disable(unsigned int cpu)
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{
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/*
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* we don't allow CPU 0 to be shutdown (it is still too special
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* e.g. clock tick interrupts)
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*/
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return cpu == 0 ? -EPERM : 0;
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}
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@ -0,0 +1,130 @@
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/*
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* linux/arch/arm/mach-realview/localtimer.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/arm_twd.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "core.h"
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#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \
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((cpu) * REALVIEW_TWD_SIZE))
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static unsigned long mpcore_timer_rate;
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/*
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* local_timer_ack: checks for a local timer interrupt.
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*
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* If a local timer interrupt has occured, acknowledge and return 1.
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* Otherwise, return 0.
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*/
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int local_timer_ack(void)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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if (__raw_readl(base + TWD_TIMER_INTSTAT)) {
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__raw_writel(1, base + TWD_TIMER_INTSTAT);
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return 1;
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}
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return 0;
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}
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void __cpuinit local_timer_setup(unsigned int cpu)
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{
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void __iomem *base = TWD_BASE(cpu);
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unsigned int load, offset;
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u64 waitjiffies;
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unsigned int count;
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/*
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* If this is the first time round, we need to work out how fast
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* the timer ticks
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*/
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if (mpcore_timer_rate == 0) {
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printk("Calibrating local timer... ");
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/* Wait for a tick to start */
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waitjiffies = get_jiffies_64() + 1;
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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/* OK, now the tick has started, let's get the timer going */
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waitjiffies += 5;
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/* enable, no interrupt or reload */
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__raw_writel(0x1, base + TWD_TIMER_CONTROL);
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/* maximum value */
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__raw_writel(0xFFFFFFFFU, base + TWD_TIMER_COUNTER);
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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count = __raw_readl(base + TWD_TIMER_COUNTER);
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mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
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printk("%lu.%02luMHz.\n", mpcore_timer_rate / 1000000,
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(mpcore_timer_rate / 100000) % 100);
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}
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load = mpcore_timer_rate / HZ;
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__raw_writel(load, base + TWD_TIMER_LOAD);
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__raw_writel(0x7, base + TWD_TIMER_CONTROL);
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/*
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* Now maneuver our local tick into the right part of the jiffy.
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* Start by working out where within the tick our local timer
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* interrupt should go.
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*/
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offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1);
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/*
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* gettimeoffset() will return a number of us since the last tick.
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* Convert this number of us to a local timer tick count.
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* Be careful of integer overflow whilst keeping maximum precision.
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*
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* with HZ=100 and 1MHz (fpga) ~ 1GHz processor:
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* load = 1 ~ 10,000
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* mpcore_timer_rate/10000 = 100 ~ 100,000
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*
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* so the multiply value will be less than 10^9 always.
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*/
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load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100;
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/* Add on our offset to get the load value */
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load = (load + offset) % (mpcore_timer_rate / HZ);
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__raw_writel(load, base + TWD_TIMER_COUNTER);
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/* Make sure our local interrupt controller has this enabled */
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__raw_writel(1 << IRQ_LOCALTIMER,
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__io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET);
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}
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/*
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* take a local timer down
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*/
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void __cpuexit local_timer_stop(unsigned int cpu)
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{
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__raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL);
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}
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@ -174,6 +174,11 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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if (max_cpus > ncores)
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max_cpus = ncores;
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/*
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* Enable the local timer for primary CPU
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*/
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local_timer_setup(cpu);
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/*
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* Initialise the possible/present maps.
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* cpu_possible_map describes the set of CPUs which may be present
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@ -61,3 +61,14 @@
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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@ -21,6 +21,9 @@
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#include <asm/arch/platform.h>
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#define IRQ_LOCALTIMER 29
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#define IRQ_LOCALWDOG 30
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/*
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* IRQ interrupts definitions are the same the INT definitions
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* held within platform.h
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@ -209,6 +209,8 @@
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#else
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#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_TWD_BASE 0x10100700
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#define REALVIEW_TWD_SIZE 0x00000100
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#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#endif
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#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
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@ -305,9 +307,6 @@
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#define INT_TSPENINT 30 /* Touchscreen pen */
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#define INT_TSKPADINT 31 /* Touchscreen keypad */
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#else
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#define INT_LOCALTIMER 29
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#define INT_LOCALWDOG 30
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#define INT_AACI 0
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#define INT_TIMERINT0_1 1
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#define INT_TIMERINT2_3 2
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