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MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.

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For Cavium CPU, we treat the same as R10000, in that all hazards
are dealt with in hardware.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2008-12-11 15:33:22 -08:00 committed by Ralf Baechle
parent 5b3b16880f
commit bd6d85c21a
1 changed files with 2 additions and 2 deletions
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4
arch/mips/include/asm/hazards.h
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@ -42,7 +42,7 @@ ASMMACRO(_ehb,
/*
* TLB hazards
*/
#if defined(CONFIG_CPU_MIPSR2)
#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* MIPSR2 defines ehb for hazard avoidance
@ -138,7 +138,7 @@ do { \
__instruction_hazard(); \
} while (0)
#elif defined(CONFIG_CPU_R10000)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.