powerpc: Merge 32-bit CHRP support.
SMP still needs more work but UP gets as far as starting userspace at least. This uses the 64-bit-style code for spinning up the cpus. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras
parent
303d72a000
commit
bbd0abda9c
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@ -339,7 +339,7 @@ config U3_DART
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default n
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config MPIC
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depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE
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depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP
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bool
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default y
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@ -207,7 +207,7 @@ turn_on_mmu:
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.globl __secondary_hold
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__secondary_hold:
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/* tell the master we're here */
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stw r3,4(0)
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stw r3,__secondary_hold_acknowledge@l(0)
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#ifdef CONFIG_SMP
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100: lwz r4,0(0)
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/* wait until we're told to start */
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@ -220,6 +220,13 @@ __secondary_hold:
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b .
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#endif /* CONFIG_SMP */
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.globl __secondary_hold_spinloop
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__secondary_hold_spinloop:
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.long 0
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.globl __secondary_hold_acknowledge
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__secondary_hold_acknowledge:
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.long -1
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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@ -1155,9 +1155,18 @@ static void __init prom_initialize_tce_table(void)
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*
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* -- Cort
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*/
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extern void __secondary_hold(void);
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extern unsigned long __secondary_hold_spinloop;
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extern unsigned long __secondary_hold_acknowledge;
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/*
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* We want to reference the copy of __secondary_hold_* in the
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* 0 - 0x100 address range
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*/
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#define LOW_ADDR(x) (((unsigned long) &(x)) & 0xff)
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static void __init prom_hold_cpus(void)
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{
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#ifdef CONFIG_PPC64
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unsigned long i;
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unsigned int reg;
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phandle node;
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@ -1166,20 +1175,18 @@ static void __init prom_hold_cpus(void)
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unsigned int interrupt_server[MAX_CPU_THREADS];
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unsigned int cpu_threads, hw_cpu_num;
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int propsize;
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extern void __secondary_hold(void);
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extern unsigned long __secondary_hold_spinloop;
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extern unsigned long __secondary_hold_acknowledge;
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struct prom_t *_prom = &RELOC(prom);
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unsigned long *spinloop
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= (void *) __pa(&__secondary_hold_spinloop);
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= (void *) LOW_ADDR(__secondary_hold_spinloop);
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unsigned long *acknowledge
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= (void *) __pa(&__secondary_hold_acknowledge);
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= (void *) LOW_ADDR(__secondary_hold_acknowledge);
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#ifdef CONFIG_PPC64
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/* __secondary_hold is actually a descriptor, not the text address */
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unsigned long secondary_hold
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= __pa(*PTRRELOC((unsigned long *)__secondary_hold));
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#else
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unsigned long secondary_hold = __pa(&__secondary_hold);
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unsigned long secondary_hold = LOW_ADDR(__secondary_hold);
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#endif
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struct prom_t *_prom = &RELOC(prom);
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prom_debug("prom_hold_cpus: start...\n");
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prom_debug(" 1) spinloop = 0x%x\n", (unsigned long)spinloop);
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@ -1197,9 +1204,8 @@ static void __init prom_hold_cpus(void)
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*spinloop = 0;
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#ifdef CONFIG_HMT
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for (i = 0; i < NR_CPUS; i++) {
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for (i = 0; i < NR_CPUS; i++)
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RELOC(hmt_thread_data)[i].pir = 0xdeadbeef;
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}
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#endif
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/* look for cpus */
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for (node = 0; prom_next_node(&node); ) {
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@ -1250,34 +1256,22 @@ static void __init prom_hold_cpus(void)
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call_prom("start-cpu", 3, 0, node,
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secondary_hold, reg);
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for ( i = 0 ; (i < 100000000) &&
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(*acknowledge == ((unsigned long)-1)); i++ )
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for (i = 0; (i < 100000000) &&
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(*acknowledge == ((unsigned long)-1)); i++ )
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mb();
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if (*acknowledge == reg) {
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if (*acknowledge == reg)
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prom_printf("done\n");
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/* We have to get every CPU out of OF,
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* even if we never start it. */
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if (cpuid >= NR_CPUS)
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goto next;
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} else {
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else
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prom_printf("failed: %x\n", *acknowledge);
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}
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}
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#ifdef CONFIG_SMP
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else
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prom_printf("%x : boot cpu %x\n", cpuid, reg);
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#endif
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next:
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#ifdef CONFIG_SMP
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/* Init paca for secondary threads. They start later. */
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for (i=1; i < cpu_threads; i++) {
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cpuid++;
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if (cpuid >= NR_CPUS)
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continue;
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}
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#endif /* CONFIG_SMP */
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cpuid++;
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/* Reserve cpu #s for secondary threads. They start later. */
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cpuid += cpu_threads;
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}
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#ifdef CONFIG_HMT
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/* Only enable HMT on processors that provide support. */
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@ -1311,7 +1305,6 @@ next:
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") exceeded: ignoring extras\n");
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prom_debug("prom_hold_cpus: end...\n");
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#endif
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}
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@ -1940,7 +1933,6 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
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unsigned long r6, unsigned long r7)
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{
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struct prom_t *_prom;
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extern char _stext[];
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unsigned long hdr;
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u32 getprop_rval;
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unsigned long offset = reloc_offset();
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@ -56,6 +56,10 @@ extern void power4_idle(void);
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boot_infos_t *boot_infos;
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struct ide_machdep_calls ppc_ide_md;
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/* XXX should go elsewhere */
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int __irq_offset_value;
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EXPORT_SYMBOL(__irq_offset_value);
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/* Used with the BI_MEMSIZE bootinfo parameter to store the memory
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size value reported by the boot loader. */
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unsigned long boot_mem_size;
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@ -5,6 +5,7 @@ ifeq ($(CONFIG_PPC64),y)
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obj-$(CONFIG_PPC_PMAC) += powermac/
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endif
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endif
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obj-$(CONFIG_PPC_CHRP) += chrp/
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obj-$(CONFIG_4xx) += 4xx/
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obj-$(CONFIG_85xx) += 85xx/
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obj-$(CONFIG_PPC_PSERIES) += pseries/
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@ -0,0 +1,3 @@
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obj-y += setup.o time.o pegasos_eth.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SMP) += smp.o
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@ -0,0 +1,310 @@
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/*
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* CHRP pci routines.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/hydra.h>
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#include <asm/prom.h>
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#include <asm/gg2.h>
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#include <asm/machdep.h>
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#include <asm/sections.h>
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#include <asm/pci-bridge.h>
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#include <asm/open_pic.h>
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#include <asm/grackle.h>
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#include <asm/rtas.h>
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/* LongTrail */
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void __iomem *gg2_pci_config_base;
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/*
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* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
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* limit the bus number to 3 bits
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*/
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int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
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int len, u32 *val)
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{
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volatile void __iomem *cfg_data;
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struct pci_controller *hose = bus->sysdata;
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if (bus->number > 7)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that off is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
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switch (len) {
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case 1:
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*val = in_8(cfg_data);
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break;
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case 2:
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*val = in_le16(cfg_data);
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break;
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default:
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*val = in_le32(cfg_data);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
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int len, u32 val)
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{
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volatile void __iomem *cfg_data;
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struct pci_controller *hose = bus->sysdata;
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if (bus->number > 7)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that off is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
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switch (len) {
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case 1:
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out_8(cfg_data, val);
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break;
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case 2:
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out_le16(cfg_data, val);
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break;
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default:
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out_le32(cfg_data, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops gg2_pci_ops =
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{
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gg2_read_config,
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gg2_write_config
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};
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/*
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* Access functions for PCI config space using RTAS calls.
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*/
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int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->index << 24);
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int ret = -1;
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int rval;
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rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
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*val = ret;
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return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
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}
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int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->index << 24);
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int rval;
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rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
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addr, len, val);
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return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops rtas_pci_ops =
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{
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rtas_read_config,
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rtas_write_config
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};
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volatile struct Hydra __iomem *Hydra = NULL;
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int __init
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hydra_init(void)
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{
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struct device_node *np;
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np = find_devices("mac-io");
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if (np == NULL || np->n_addrs == 0)
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return 0;
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Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
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printk("Hydra Mac I/O at %lx\n", np->addrs[0].address);
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printk("Hydra Feature_Control was %x",
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in_le32(&Hydra->Feature_Control));
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out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
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HYDRA_FC_SCSI_CELL_EN |
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HYDRA_FC_SCCA_ENABLE |
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HYDRA_FC_SCCB_ENABLE |
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HYDRA_FC_ARB_BYPASS |
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HYDRA_FC_MPIC_ENABLE |
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HYDRA_FC_SLOW_SCC_PCLK |
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HYDRA_FC_MPIC_IS_MASTER));
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printk(", now %x\n", in_le32(&Hydra->Feature_Control));
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return 1;
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}
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void __init
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chrp_pcibios_fixup(void)
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{
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struct pci_dev *dev = NULL;
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struct device_node *np;
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/* PCI interrupts are controlled by the OpenPIC */
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for_each_pci_dev(dev) {
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np = pci_device_to_OF_node(dev);
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if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
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dev->irq = np->intrs[0].line;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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}
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}
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#define PRG_CL_RESET_VALID 0x00010000
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static void __init
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setup_python(struct pci_controller *hose, struct device_node *dev)
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{
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u32 __iomem *reg;
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u32 val;
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unsigned long addr = dev->addrs[0].address;
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setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
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/* Clear the magic go-slow bit */
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reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
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val = in_be32(®[12]);
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if (val & PRG_CL_RESET_VALID) {
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out_be32(®[12], val & ~PRG_CL_RESET_VALID);
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in_be32(®[12]);
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}
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iounmap(reg);
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}
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/* Marvell Discovery II based Pegasos 2 */
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static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
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{
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struct device_node *root = find_path_device("/");
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struct device_node *rtas;
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rtas = of_find_node_by_name (root, "rtas");
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if (rtas) {
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hose->ops = &rtas_pci_ops;
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} else {
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printk ("RTAS supporting Pegasos OF not found, please upgrade"
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" your firmware\n");
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}
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pci_assign_all_buses = 1;
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}
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void __init
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chrp_find_bridges(void)
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{
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struct device_node *dev;
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int *bus_range;
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int len, index = -1;
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struct pci_controller *hose;
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unsigned int *dma;
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char *model, *machine;
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int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
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struct device_node *root = find_path_device("/");
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/*
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* The PCI host bridge nodes on some machines don't have
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* properties to adequately identify them, so we have to
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* look at what sort of machine this is as well.
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*/
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machine = get_property(root, "model", NULL);
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if (machine != NULL) {
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is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
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is_mot = strncmp(machine, "MOT", 3) == 0;
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if (strncmp(machine, "Pegasos2", 8) == 0)
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is_pegasos = 2;
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else if (strncmp(machine, "Pegasos", 7) == 0)
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is_pegasos = 1;
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}
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for (dev = root->child; dev != NULL; dev = dev->sibling) {
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if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
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continue;
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++index;
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/* The GG2 bridge on the LongTrail doesn't have an address */
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if (dev->n_addrs < 1 && !is_longtrail) {
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printk(KERN_WARNING "Can't use %s: no address\n",
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dev->full_name);
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continue;
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}
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bus_range = (int *) get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s\n",
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dev->full_name);
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continue;
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}
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if (bus_range[1] == bus_range[0])
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printk(KERN_INFO "PCI bus %d", bus_range[0]);
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else
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printk(KERN_INFO "PCI buses %d..%d",
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bus_range[0], bus_range[1]);
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printk(" controlled by %s", dev->type);
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if (dev->n_addrs > 0)
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printk(" at %lx", dev->addrs[0].address);
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printk("\n");
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hose = pcibios_alloc_controller();
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if (!hose) {
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printk("Can't allocate PCI controller structure for %s\n",
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dev->full_name);
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continue;
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}
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hose->arch_data = dev;
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hose->first_busno = bus_range[0];
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hose->last_busno = bus_range[1];
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model = get_property(dev, "model", NULL);
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if (model == NULL)
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model = "<none>";
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if (device_is_compatible(dev, "IBM,python")) {
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setup_python(hose, dev);
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} else if (is_mot
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|| strncmp(model, "Motorola, Grackle", 17) == 0) {
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setup_grackle(hose);
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} else if (is_longtrail) {
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||||
void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
|
||||
hose->ops = &gg2_pci_ops;
|
||||
hose->cfg_data = p;
|
||||
gg2_pci_config_base = p;
|
||||
} else if (is_pegasos == 1) {
|
||||
setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
|
||||
} else if (is_pegasos == 2) {
|
||||
setup_peg2(hose, dev);
|
||||
} else {
|
||||
printk("No methods for %s (model %s), using RTAS\n",
|
||||
dev->full_name, model);
|
||||
hose->ops = &rtas_pci_ops;
|
||||
}
|
||||
|
||||
pci_process_bridge_OF_ranges(hose, dev, index == 0);
|
||||
|
||||
/* check the first bridge for a property that we can
|
||||
use to set pci_dram_offset */
|
||||
dma = (unsigned int *)
|
||||
get_property(dev, "ibm,dma-ranges", &len);
|
||||
if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
|
||||
pci_dram_offset = dma[2] - dma[3];
|
||||
printk("pci_dram_offset = %lx\n", pci_dram_offset);
|
||||
}
|
||||
}
|
||||
|
||||
/* Do not fixup interrupts from OF tree on pegasos */
|
||||
if (is_pegasos == 0)
|
||||
ppc_md.pcibios_fixup = chrp_pcibios_fixup;
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* arch/ppc/platforms/chrp_pegasos_eth.c
|
||||
*
|
||||
* Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
|
||||
* Thanks to :
|
||||
* Dale Farnsworth <dale@farnsworth.org>
|
||||
* Mark A. Greer <mgreer@mvista.com>
|
||||
* Nicolas DET <nd@bplan-gmbh.de>
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
* And anyone else who helped me on this.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/mv643xx.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
/* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
|
||||
static struct resource mv643xx_eth_shared_resources[] = {
|
||||
[0] = {
|
||||
.name = "ethernet shared base",
|
||||
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
|
||||
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
|
||||
MV643XX_ETH_SHARED_REGS_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mv643xx_eth_shared_device = {
|
||||
.name = MV643XX_ETH_SHARED_NAME,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
|
||||
.resource = mv643xx_eth_shared_resources,
|
||||
};
|
||||
|
||||
static struct resource mv643xx_eth0_resources[] = {
|
||||
[0] = {
|
||||
.name = "eth0 irq",
|
||||
.start = 9,
|
||||
.end = 9,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data eth0_pd;
|
||||
|
||||
static struct platform_device eth0_device = {
|
||||
.name = MV643XX_ETH_NAME,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
|
||||
.resource = mv643xx_eth0_resources,
|
||||
.dev = {
|
||||
.platform_data = ð0_pd,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource mv643xx_eth1_resources[] = {
|
||||
[0] = {
|
||||
.name = "eth1 irq",
|
||||
.start = 9,
|
||||
.end = 9,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data eth1_pd;
|
||||
|
||||
static struct platform_device eth1_device = {
|
||||
.name = MV643XX_ETH_NAME,
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
|
||||
.resource = mv643xx_eth1_resources,
|
||||
.dev = {
|
||||
.platform_data = ð1_pd,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
|
||||
&mv643xx_eth_shared_device,
|
||||
ð0_device,
|
||||
ð1_device,
|
||||
};
|
||||
|
||||
|
||||
int
|
||||
mv643xx_eth_add_pds(void)
|
||||
{
|
||||
int ret = 0;
|
||||
static struct pci_device_id pci_marvell_mv64360[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
|
||||
{ }
|
||||
};
|
||||
|
||||
if (pci_dev_present(pci_marvell_mv64360)) {
|
||||
ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
device_initcall(mv643xx_eth_add_pds);
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
/*
|
||||
* arch/ppc/platforms/setup.c
|
||||
*
|
||||
* Copyright (C) 1995 Linus Torvalds
|
||||
* Adapted from 'alpha' version by Gary Thomas
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
||||
*/
|
||||
|
||||
/*
|
||||
* bootup setup stuff..
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/a.out.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/adb.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/ide.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/gg2.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/hydra.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/btext.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/rtas.h>
|
||||
#include <asm/xmon.h>
|
||||
|
||||
void chrp_get_rtc_time(struct rtc_time *);
|
||||
int chrp_set_rtc_time(struct rtc_time *);
|
||||
void chrp_calibrate_decr(void);
|
||||
long chrp_time_init(void);
|
||||
|
||||
void chrp_find_bridges(void);
|
||||
void chrp_event_scan(void);
|
||||
void rtas_indicator_progress(char *, unsigned short);
|
||||
void btext_progress(char *, unsigned short);
|
||||
|
||||
int _chrp_type;
|
||||
EXPORT_SYMBOL(_chrp_type);
|
||||
|
||||
struct mpic *chrp_mpic;
|
||||
|
||||
/*
|
||||
* XXX this should be in xmon.h, but putting it there means xmon.h
|
||||
* has to include <linux/interrupt.h> (to get irqreturn_t), which
|
||||
* causes all sorts of problems. -- paulus
|
||||
*/
|
||||
extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
|
||||
|
||||
extern unsigned long loops_per_jiffy;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t chrp_smp_ops;
|
||||
#endif
|
||||
|
||||
static const char *gg2_memtypes[4] = {
|
||||
"FPM", "SDRAM", "EDO", "BEDO"
|
||||
};
|
||||
static const char *gg2_cachesizes[4] = {
|
||||
"256 KB", "512 KB", "1 MB", "Reserved"
|
||||
};
|
||||
static const char *gg2_cachetypes[4] = {
|
||||
"Asynchronous", "Reserved", "Flow-Through Synchronous",
|
||||
"Pipelined Synchronous"
|
||||
};
|
||||
static const char *gg2_cachemodes[4] = {
|
||||
"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
|
||||
};
|
||||
|
||||
void chrp_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
int i, sdramen;
|
||||
unsigned int t;
|
||||
struct device_node *root;
|
||||
const char *model = "";
|
||||
|
||||
root = find_path_device("/");
|
||||
if (root)
|
||||
model = get_property(root, "model", NULL);
|
||||
seq_printf(m, "machine\t\t: CHRP %s\n", model);
|
||||
|
||||
/* longtrail (goldengate) stuff */
|
||||
if (!strncmp(model, "IBM,LongTrail", 13)) {
|
||||
/* VLSI VAS96011/12 `Golden Gate 2' */
|
||||
/* Memory banks */
|
||||
sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
|
||||
>>31) & 1;
|
||||
for (i = 0; i < (sdramen ? 4 : 6); i++) {
|
||||
t = in_le32(gg2_pci_config_base+
|
||||
GG2_PCI_DRAM_BANK0+
|
||||
i*4);
|
||||
if (!(t & 1))
|
||||
continue;
|
||||
switch ((t>>8) & 0x1f) {
|
||||
case 0x1f:
|
||||
model = "4 MB";
|
||||
break;
|
||||
case 0x1e:
|
||||
model = "8 MB";
|
||||
break;
|
||||
case 0x1c:
|
||||
model = "16 MB";
|
||||
break;
|
||||
case 0x18:
|
||||
model = "32 MB";
|
||||
break;
|
||||
case 0x10:
|
||||
model = "64 MB";
|
||||
break;
|
||||
case 0x00:
|
||||
model = "128 MB";
|
||||
break;
|
||||
default:
|
||||
model = "Reserved";
|
||||
break;
|
||||
}
|
||||
seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
|
||||
gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
|
||||
}
|
||||
/* L2 cache */
|
||||
t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
|
||||
seq_printf(m, "board l2\t: %s %s (%s)\n",
|
||||
gg2_cachesizes[(t>>7) & 3],
|
||||
gg2_cachetypes[(t>>2) & 3],
|
||||
gg2_cachemodes[t & 3]);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Fixes for the National Semiconductor PC78308VUL SuperI/O
|
||||
*
|
||||
* Some versions of Open Firmware incorrectly initialize the IRQ settings
|
||||
* for keyboard and mouse
|
||||
*/
|
||||
static inline void __init sio_write(u8 val, u8 index)
|
||||
{
|
||||
outb(index, 0x15c);
|
||||
outb(val, 0x15d);
|
||||
}
|
||||
|
||||
static inline u8 __init sio_read(u8 index)
|
||||
{
|
||||
outb(index, 0x15c);
|
||||
return inb(0x15d);
|
||||
}
|
||||
|
||||
static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
|
||||
u8 type)
|
||||
{
|
||||
u8 level0, type0, active;
|
||||
|
||||
/* select logical device */
|
||||
sio_write(device, 0x07);
|
||||
active = sio_read(0x30);
|
||||
level0 = sio_read(0x70);
|
||||
type0 = sio_read(0x71);
|
||||
if (level0 != level || type0 != type || !active) {
|
||||
printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
|
||||
"remapping to level %d, type %d, active\n",
|
||||
name, level0, type0, !active ? "in" : "", level, type);
|
||||
sio_write(0x01, 0x30);
|
||||
sio_write(level, 0x70);
|
||||
sio_write(type, 0x71);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init sio_init(void)
|
||||
{
|
||||
struct device_node *root;
|
||||
|
||||
if ((root = find_path_device("/")) &&
|
||||
!strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) {
|
||||
/* logical device 0 (KBC/Keyboard) */
|
||||
sio_fixup_irq("keyboard", 0, 1, 2);
|
||||
/* select logical device 1 (KBC/Mouse) */
|
||||
sio_fixup_irq("mouse", 1, 12, 2);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void __init pegasos_set_l2cr(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
|
||||
if (_chrp_type != _CHRP_Pegasos)
|
||||
return;
|
||||
|
||||
/* Enable L2 cache if needed */
|
||||
np = find_type_devices("cpu");
|
||||
if (np != NULL) {
|
||||
unsigned int *l2cr = (unsigned int *)
|
||||
get_property (np, "l2cr", NULL);
|
||||
if (l2cr == NULL) {
|
||||
printk ("Pegasos l2cr : no cpu l2cr property found\n");
|
||||
return;
|
||||
}
|
||||
if (!((*l2cr) & 0x80000000)) {
|
||||
printk ("Pegasos l2cr : L2 cache was not active, "
|
||||
"activating\n");
|
||||
_set_L2CR(0);
|
||||
_set_L2CR((*l2cr) | 0x80000000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init chrp_setup_arch(void)
|
||||
{
|
||||
struct device_node *root = find_path_device ("/");
|
||||
char *machine = NULL;
|
||||
struct device_node *device;
|
||||
unsigned int *p = NULL;
|
||||
|
||||
/* init to some ~sane value until calibrate_delay() runs */
|
||||
loops_per_jiffy = 50000000/HZ;
|
||||
|
||||
if (root)
|
||||
machine = get_property(root, "model", NULL);
|
||||
if (machine && strncmp(machine, "Pegasos", 7) == 0) {
|
||||
_chrp_type = _CHRP_Pegasos;
|
||||
} else if (machine && strncmp(machine, "IBM", 3) == 0) {
|
||||
_chrp_type = _CHRP_IBM;
|
||||
} else if (machine && strncmp(machine, "MOT", 3) == 0) {
|
||||
_chrp_type = _CHRP_Motorola;
|
||||
} else {
|
||||
/* Let's assume it is an IBM chrp if all else fails */
|
||||
_chrp_type = _CHRP_IBM;
|
||||
}
|
||||
printk("chrp type = %x\n", _chrp_type);
|
||||
|
||||
rtas_initialize();
|
||||
if (rtas_token("display-character") >= 0)
|
||||
ppc_md.progress = rtas_progress;
|
||||
|
||||
#ifdef CONFIG_BOOTX_TEXT
|
||||
if (ppc_md.progress == NULL && boot_text_mapped)
|
||||
ppc_md.progress = btext_progress;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
/* this is fine for chrp */
|
||||
initrd_below_start_ok = 1;
|
||||
|
||||
if (initrd_start)
|
||||
ROOT_DEV = Root_RAM0;
|
||||
else
|
||||
#endif
|
||||
ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
|
||||
|
||||
/* On pegasos, enable the L2 cache if not already done by OF */
|
||||
pegasos_set_l2cr();
|
||||
|
||||
/* Lookup PCI host bridges */
|
||||
chrp_find_bridges();
|
||||
|
||||
/*
|
||||
* Temporary fixes for PCI devices.
|
||||
* -- Geert
|
||||
*/
|
||||
hydra_init(); /* Mac I/O */
|
||||
|
||||
/*
|
||||
* Fix the Super I/O configuration
|
||||
*/
|
||||
sio_init();
|
||||
|
||||
/* Get the event scan rate for the rtas so we know how
|
||||
* often it expects a heartbeat. -- Cort
|
||||
*/
|
||||
device = find_devices("rtas");
|
||||
if (device)
|
||||
p = (unsigned int *) get_property
|
||||
(device, "rtas-event-scan-rate", NULL);
|
||||
if (p && *p) {
|
||||
ppc_md.heartbeat = chrp_event_scan;
|
||||
ppc_md.heartbeat_reset = HZ / (*p * 30) - 1;
|
||||
ppc_md.heartbeat_count = 1;
|
||||
printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
|
||||
*p, ppc_md.heartbeat_reset);
|
||||
}
|
||||
|
||||
pci_create_OF_bus_map();
|
||||
|
||||
/*
|
||||
* Print the banner, then scroll down so boot progress
|
||||
* can be printed. -- Cort
|
||||
*/
|
||||
if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
|
||||
}
|
||||
|
||||
void
|
||||
chrp_event_scan(void)
|
||||
{
|
||||
unsigned char log[1024];
|
||||
int ret = 0;
|
||||
|
||||
/* XXX: we should loop until the hardware says no more error logs -- Cort */
|
||||
rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
|
||||
__pa(log), 1024);
|
||||
ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
|
||||
}
|
||||
|
||||
/*
|
||||
* Finds the open-pic node and sets up the mpic driver.
|
||||
*/
|
||||
static void __init chrp_find_openpic(void)
|
||||
{
|
||||
struct device_node *np, *root;
|
||||
int len, i, j, irq_count;
|
||||
int isu_size, idu_size;
|
||||
unsigned int *iranges, *opprop = NULL;
|
||||
int oplen = 0;
|
||||
unsigned long opaddr;
|
||||
int na = 1;
|
||||
unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS];
|
||||
|
||||
np = find_type_devices("open-pic");
|
||||
if (np == NULL)
|
||||
return;
|
||||
root = find_path_device("/");
|
||||
if (root) {
|
||||
opprop = (unsigned int *) get_property
|
||||
(root, "platform-open-pic", &oplen);
|
||||
na = prom_n_addr_cells(root);
|
||||
}
|
||||
if (opprop && oplen >= na * sizeof(unsigned int)) {
|
||||
opaddr = opprop[na-1]; /* assume 32-bit */
|
||||
oplen /= na * sizeof(unsigned int);
|
||||
} else {
|
||||
if (np->n_addrs == 0)
|
||||
return;
|
||||
opaddr = np->addrs[0].address;
|
||||
oplen = 0;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
|
||||
|
||||
irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */
|
||||
prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS - 4);
|
||||
|
||||
iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len);
|
||||
if (iranges == NULL)
|
||||
len = 0; /* non-distributed mpic */
|
||||
else
|
||||
len /= 2 * sizeof(unsigned int);
|
||||
|
||||
/*
|
||||
* The first pair of cells in interrupt-ranges refers to the
|
||||
* IDU; subsequent pairs refer to the ISUs.
|
||||
*/
|
||||
if (oplen < len) {
|
||||
printk(KERN_ERR "Insufficient addresses for distributed"
|
||||
" OpenPIC (%d < %d)\n", np->n_addrs, len);
|
||||
len = oplen;
|
||||
}
|
||||
|
||||
isu_size = 0;
|
||||
idu_size = 0;
|
||||
if (len > 0 && iranges[1] != 0) {
|
||||
printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
|
||||
iranges[0], iranges[0] + iranges[1] - 1);
|
||||
idu_size = iranges[1];
|
||||
}
|
||||
if (len > 1)
|
||||
isu_size = iranges[3];
|
||||
|
||||
chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY,
|
||||
isu_size, NUM_ISA_INTERRUPTS, irq_count,
|
||||
NR_IRQS - 4, init_senses, irq_count,
|
||||
" MPIC ");
|
||||
if (chrp_mpic == NULL) {
|
||||
printk(KERN_ERR "Failed to allocate MPIC structure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
j = na - 1;
|
||||
for (i = 1; i < len; ++i) {
|
||||
iranges += 2;
|
||||
j += na;
|
||||
printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
|
||||
iranges[0], iranges[0] + iranges[1] - 1,
|
||||
opprop[j]);
|
||||
mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
|
||||
}
|
||||
|
||||
mpic_init(chrp_mpic);
|
||||
mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
|
||||
static struct irqaction xmon_irqaction = {
|
||||
.handler = xmon_irq,
|
||||
.mask = CPU_MASK_NONE,
|
||||
.name = "XMON break",
|
||||
};
|
||||
#endif
|
||||
|
||||
void __init chrp_init_IRQ(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned long chrp_int_ack = 0;
|
||||
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
|
||||
struct device_node *kbd;
|
||||
#endif
|
||||
|
||||
for (np = find_devices("pci"); np != NULL; np = np->next) {
|
||||
unsigned int *addrp = (unsigned int *)
|
||||
get_property(np, "8259-interrupt-acknowledge", NULL);
|
||||
|
||||
if (addrp == NULL)
|
||||
continue;
|
||||
chrp_int_ack = addrp[prom_n_addr_cells(np)-1];
|
||||
break;
|
||||
}
|
||||
if (np == NULL)
|
||||
printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
|
||||
|
||||
chrp_find_openpic();
|
||||
|
||||
i8259_init(chrp_int_ack, 0);
|
||||
|
||||
if (_chrp_type == _CHRP_Pegasos)
|
||||
ppc_md.get_irq = i8259_irq;
|
||||
else
|
||||
ppc_md.get_irq = mpic_get_irq;
|
||||
|
||||
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
|
||||
/* see if there is a keyboard in the device tree
|
||||
with a parent of type "adb" */
|
||||
for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next)
|
||||
if (kbd->parent && kbd->parent->type
|
||||
&& strcmp(kbd->parent->type, "adb") == 0)
|
||||
break;
|
||||
if (kbd)
|
||||
setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init
|
||||
chrp_init2(void)
|
||||
{
|
||||
request_region(0x20,0x20,"pic1");
|
||||
request_region(0xa0,0x20,"pic2");
|
||||
request_region(0x00,0x20,"dma1");
|
||||
request_region(0x40,0x20,"timer");
|
||||
request_region(0x80,0x10,"dma page reg");
|
||||
request_region(0xc0,0x20,"dma2");
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress(" Have fun! ", 0x7777);
|
||||
}
|
||||
|
||||
void __init chrp_init(void)
|
||||
{
|
||||
ISA_DMA_THRESHOLD = ~0L;
|
||||
DMA_MODE_READ = 0x44;
|
||||
DMA_MODE_WRITE = 0x48;
|
||||
isa_io_base = CHRP_ISA_IO_BASE; /* default value */
|
||||
ppc_do_canonicalize_irqs = 1;
|
||||
|
||||
/* Assume we have an 8259... */
|
||||
__irq_offset_value = NUM_ISA_INTERRUPTS;
|
||||
|
||||
ppc_md.setup_arch = chrp_setup_arch;
|
||||
ppc_md.show_cpuinfo = chrp_show_cpuinfo;
|
||||
|
||||
ppc_md.init_IRQ = chrp_init_IRQ;
|
||||
ppc_md.init = chrp_init2;
|
||||
|
||||
ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
|
||||
|
||||
ppc_md.restart = rtas_restart;
|
||||
ppc_md.power_off = rtas_power_off;
|
||||
ppc_md.halt = rtas_halt;
|
||||
|
||||
ppc_md.time_init = chrp_time_init;
|
||||
ppc_md.set_rtc_time = chrp_set_rtc_time;
|
||||
ppc_md.get_rtc_time = chrp_get_rtc_time;
|
||||
ppc_md.calibrate_decr = chrp_calibrate_decr;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_ops = &chrp_smp_ops;
|
||||
#endif /* CONFIG_SMP */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOOTX_TEXT
|
||||
void
|
||||
btext_progress(char *s, unsigned short hex)
|
||||
{
|
||||
btext_drawstring(s);
|
||||
btext_drawstring("\n");
|
||||
}
|
||||
#endif /* CONFIG_BOOTX_TEXT */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Smp support for CHRP machines.
|
||||
*
|
||||
* Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
|
||||
* deal of code from the sparc and intel versions.
|
||||
*
|
||||
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/smp_lock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/residual.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/open_pic.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
extern unsigned long smp_chrp_cpu_nr;
|
||||
|
||||
static int __init smp_chrp_probe(void)
|
||||
{
|
||||
if (smp_chrp_cpu_nr > 1)
|
||||
openpic_request_IPIs();
|
||||
|
||||
return smp_chrp_cpu_nr;
|
||||
}
|
||||
|
||||
static void __devinit smp_chrp_kick_cpu(int nr)
|
||||
{
|
||||
*(unsigned long *)KERNELBASE = nr;
|
||||
asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
|
||||
}
|
||||
|
||||
static void __devinit smp_chrp_setup_cpu(int cpu_nr)
|
||||
{
|
||||
if (OpenPIC_Addr)
|
||||
do_openpic_setup_cpu();
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(timebase_lock);
|
||||
static unsigned int timebase_upper = 0, timebase_lower = 0;
|
||||
|
||||
void __devinit smp_chrp_give_timebase(void)
|
||||
{
|
||||
spin_lock(&timebase_lock);
|
||||
rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
|
||||
timebase_upper = get_tbu();
|
||||
timebase_lower = get_tbl();
|
||||
spin_unlock(&timebase_lock);
|
||||
|
||||
while (timebase_upper || timebase_lower)
|
||||
barrier();
|
||||
rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
|
||||
}
|
||||
|
||||
void __devinit smp_chrp_take_timebase(void)
|
||||
{
|
||||
while (!(timebase_upper || timebase_lower))
|
||||
barrier();
|
||||
spin_lock(&timebase_lock);
|
||||
set_tb(timebase_upper, timebase_lower);
|
||||
timebase_upper = 0;
|
||||
timebase_lower = 0;
|
||||
spin_unlock(&timebase_lock);
|
||||
printk("CPU %i taken timebase\n", smp_processor_id());
|
||||
}
|
||||
|
||||
/* CHRP with openpic */
|
||||
struct smp_ops_t chrp_smp_ops = {
|
||||
.message_pass = smp_openpic_message_pass,
|
||||
.probe = smp_chrp_probe,
|
||||
.kick_cpu = smp_chrp_kick_cpu,
|
||||
.setup_cpu = smp_chrp_setup_cpu,
|
||||
.give_timebase = smp_chrp_give_timebase,
|
||||
.take_timebase = smp_chrp_take_timebase,
|
||||
};
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* arch/ppc/platforms/chrp_time.c
|
||||
*
|
||||
* Copyright (C) 1991, 1992, 1995 Linus Torvalds
|
||||
*
|
||||
* Adapted for PowerPC (PReP) by Gary Thomas
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu).
|
||||
* Copied and modified from arch/i386/kernel/time.c
|
||||
*
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/bcd.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/nvram.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
extern spinlock_t rtc_lock;
|
||||
|
||||
static int nvram_as1 = NVRAM_AS1;
|
||||
static int nvram_as0 = NVRAM_AS0;
|
||||
static int nvram_data = NVRAM_DATA;
|
||||
|
||||
long __init chrp_time_init(void)
|
||||
{
|
||||
struct device_node *rtcs;
|
||||
int base;
|
||||
|
||||
rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
|
||||
if (rtcs == NULL)
|
||||
rtcs = find_compatible_devices("rtc", "ds1385-rtc");
|
||||
if (rtcs == NULL || rtcs->addrs == NULL)
|
||||
return 0;
|
||||
base = rtcs->addrs[0].address;
|
||||
nvram_as1 = 0;
|
||||
nvram_as0 = base;
|
||||
nvram_data = base + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int chrp_cmos_clock_read(int addr)
|
||||
{
|
||||
if (nvram_as1 != 0)
|
||||
outb(addr>>8, nvram_as1);
|
||||
outb(addr, nvram_as0);
|
||||
return (inb(nvram_data));
|
||||
}
|
||||
|
||||
void chrp_cmos_clock_write(unsigned long val, int addr)
|
||||
{
|
||||
if (nvram_as1 != 0)
|
||||
outb(addr>>8, nvram_as1);
|
||||
outb(addr, nvram_as0);
|
||||
outb(val, nvram_data);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the hardware clock. -- Cort
|
||||
*/
|
||||
int chrp_set_rtc_time(struct rtc_time *tmarg)
|
||||
{
|
||||
unsigned char save_control, save_freq_select;
|
||||
struct rtc_time tm = *tmarg;
|
||||
|
||||
spin_lock(&rtc_lock);
|
||||
|
||||
save_control = chrp_cmos_clock_read(RTC_CONTROL); /* tell the clock it's being set */
|
||||
|
||||
chrp_cmos_clock_write((save_control|RTC_SET), RTC_CONTROL);
|
||||
|
||||
save_freq_select = chrp_cmos_clock_read(RTC_FREQ_SELECT); /* stop and reset prescaler */
|
||||
|
||||
chrp_cmos_clock_write((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
|
||||
|
||||
tm.tm_year -= 1900;
|
||||
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
|
||||
BIN_TO_BCD(tm.tm_sec);
|
||||
BIN_TO_BCD(tm.tm_min);
|
||||
BIN_TO_BCD(tm.tm_hour);
|
||||
BIN_TO_BCD(tm.tm_mon);
|
||||
BIN_TO_BCD(tm.tm_mday);
|
||||
BIN_TO_BCD(tm.tm_year);
|
||||
}
|
||||
chrp_cmos_clock_write(tm.tm_sec,RTC_SECONDS);
|
||||
chrp_cmos_clock_write(tm.tm_min,RTC_MINUTES);
|
||||
chrp_cmos_clock_write(tm.tm_hour,RTC_HOURS);
|
||||
chrp_cmos_clock_write(tm.tm_mon,RTC_MONTH);
|
||||
chrp_cmos_clock_write(tm.tm_mday,RTC_DAY_OF_MONTH);
|
||||
chrp_cmos_clock_write(tm.tm_year,RTC_YEAR);
|
||||
|
||||
/* The following flags have to be released exactly in this order,
|
||||
* otherwise the DS12887 (popular MC146818A clone with integrated
|
||||
* battery and quartz) will not reset the oscillator and will not
|
||||
* update precisely 500 ms later. You won't find this mentioned in
|
||||
* the Dallas Semiconductor data sheets, but who believes data
|
||||
* sheets anyway ... -- Markus Kuhn
|
||||
*/
|
||||
chrp_cmos_clock_write(save_control, RTC_CONTROL);
|
||||
chrp_cmos_clock_write(save_freq_select, RTC_FREQ_SELECT);
|
||||
|
||||
spin_unlock(&rtc_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void chrp_get_rtc_time(struct rtc_time *tm)
|
||||
{
|
||||
unsigned int year, mon, day, hour, min, sec;
|
||||
int uip, i;
|
||||
|
||||
/* The Linux interpretation of the CMOS clock register contents:
|
||||
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
|
||||
* RTC registers show the second which has precisely just started.
|
||||
* Let's hope other operating systems interpret the RTC the same way.
|
||||
*/
|
||||
|
||||
/* Since the UIP flag is set for about 2.2 ms and the clock
|
||||
* is typically written with a precision of 1 jiffy, trying
|
||||
* to obtain a precision better than a few milliseconds is
|
||||
* an illusion. Only consistency is interesting, this also
|
||||
* allows to use the routine for /dev/rtc without a potential
|
||||
* 1 second kernel busy loop triggered by any reader of /dev/rtc.
|
||||
*/
|
||||
|
||||
for ( i = 0; i<1000000; i++) {
|
||||
uip = chrp_cmos_clock_read(RTC_FREQ_SELECT);
|
||||
sec = chrp_cmos_clock_read(RTC_SECONDS);
|
||||
min = chrp_cmos_clock_read(RTC_MINUTES);
|
||||
hour = chrp_cmos_clock_read(RTC_HOURS);
|
||||
day = chrp_cmos_clock_read(RTC_DAY_OF_MONTH);
|
||||
mon = chrp_cmos_clock_read(RTC_MONTH);
|
||||
year = chrp_cmos_clock_read(RTC_YEAR);
|
||||
uip |= chrp_cmos_clock_read(RTC_FREQ_SELECT);
|
||||
if ((uip & RTC_UIP)==0) break;
|
||||
}
|
||||
|
||||
if (!(chrp_cmos_clock_read(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
|
||||
BCD_TO_BIN(sec);
|
||||
BCD_TO_BIN(min);
|
||||
BCD_TO_BIN(hour);
|
||||
BCD_TO_BIN(day);
|
||||
BCD_TO_BIN(mon);
|
||||
BCD_TO_BIN(year);
|
||||
}
|
||||
if ((year += 1900) < 1970)
|
||||
year += 100;
|
||||
tm->tm_sec = sec;
|
||||
tm->tm_min = min;
|
||||
tm->tm_hour = hour;
|
||||
tm->tm_mday = day;
|
||||
tm->tm_mon = mon;
|
||||
tm->tm_year = year;
|
||||
}
|
||||
|
||||
|
||||
void __init chrp_calibrate_decr(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
unsigned int freq, *fp;
|
||||
|
||||
/*
|
||||
* The cpu node should have a timebase-frequency property
|
||||
* to tell us the rate at which the decrementer counts.
|
||||
*/
|
||||
freq = 16666000; /* hardcoded default */
|
||||
cpu = find_type_devices("cpu");
|
||||
if (cpu != 0) {
|
||||
fp = (unsigned int *)
|
||||
get_property(cpu, "timebase-frequency", NULL);
|
||||
if (fp != 0)
|
||||
freq = *fp;
|
||||
}
|
||||
ppc_tb_freq = freq;
|
||||
}
|
||||
|
|
@ -71,10 +71,6 @@ static u32 level_mask[4];
|
|||
|
||||
static DEFINE_SPINLOCK(pmac_pic_lock);
|
||||
|
||||
/* XXX here for now, should move to arch/powerpc/kernel/irq.c */
|
||||
int ppc_do_canonicalize_irqs;
|
||||
EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
|
||||
|
||||
#define GATWICK_IRQ_POOL_SIZE 10
|
||||
static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
|
||||
|
||||
|
|
|
|||
Reference in New Issue