powerpc/512x: add MPC8308 dma support
MPC8308 has pretty much the same DMA controller as MPC5121 and this patch adds support for MPC8308 to the mpc512x_dma driver. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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2862559e8a
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2 changed files with 68 additions and 21 deletions
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@ -109,7 +109,7 @@ config FSL_DMA
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config MPC512X_DMA
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tristate "Freescale MPC512x built-in DMA engine support"
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depends on PPC_MPC512x
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depends on PPC_MPC512x || PPC_MPC831x
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select DMA_ENGINE
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---help---
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Enable support for the Freescale MPC512x built-in DMA engine.
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@ -1,6 +1,7 @@
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/*
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* Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
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* Copyright (C) Semihalf 2009
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010
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*
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* Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
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* (defines, structures and comments) was taken from MPC5121 DMA driver
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@ -70,6 +71,8 @@
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#define MPC_DMA_DMAES_SBE (1 << 1)
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#define MPC_DMA_DMAES_DBE (1 << 0)
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#define MPC_DMA_DMAGPOR_SNOOP_ENABLE (1 << 6)
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#define MPC_DMA_TSIZE_1 0x00
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#define MPC_DMA_TSIZE_2 0x01
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#define MPC_DMA_TSIZE_4 0x02
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@ -104,7 +107,10 @@ struct __attribute__ ((__packed__)) mpc_dma_regs {
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/* 0x30 */
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u32 dmahrsh; /* DMA hw request status high(ch63~32) */
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u32 dmahrsl; /* DMA hardware request status low(ch31~0) */
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u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
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union {
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u32 dmaihsa; /* DMA interrupt high select AXE(ch63~32) */
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u32 dmagpor; /* (General purpose register on MPC8308) */
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};
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u32 dmailsa; /* DMA interrupt low select AXE(ch31~0) */
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/* 0x40 ~ 0xff */
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u32 reserve0[48]; /* Reserved */
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@ -195,7 +201,9 @@ struct mpc_dma {
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struct mpc_dma_regs __iomem *regs;
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struct mpc_dma_tcd __iomem *tcd;
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int irq;
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int irq2;
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uint error_status;
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int is_mpc8308;
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/* Lock for error_status field in this structure */
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spinlock_t error_status_lock;
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@ -307,8 +315,10 @@ static irqreturn_t mpc_dma_irq(int irq, void *data)
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spin_unlock(&mdma->error_status_lock);
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/* Handle interrupt on each channel */
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mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
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if (mdma->dma.chancnt > 32) {
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mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
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in_be32(&mdma->regs->dmaerrh), 32);
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}
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mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
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in_be32(&mdma->regs->dmaerrl), 0);
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@ -562,6 +572,7 @@ static struct dma_async_tx_descriptor *
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mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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size_t len, unsigned long flags)
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{
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struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
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struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
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struct mpc_dma_desc *mdesc = NULL;
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struct mpc_dma_tcd *tcd;
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@ -590,7 +601,8 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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tcd->dsize = MPC_DMA_TSIZE_32;
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tcd->soff = 32;
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tcd->doff = 32;
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} else if (IS_ALIGNED(src | dst | len, 16)) {
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} else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) {
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/* MPC8308 doesn't support 16 byte transfers */
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tcd->ssize = MPC_DMA_TSIZE_16;
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tcd->dsize = MPC_DMA_TSIZE_16;
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tcd->soff = 16;
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@ -650,6 +662,15 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
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return -EINVAL;
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}
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if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) {
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mdma->is_mpc8308 = 1;
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mdma->irq2 = irq_of_parse_and_map(dn, 1);
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if (mdma->irq2 == NO_IRQ) {
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dev_err(dev, "Error mapping IRQ!\n");
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return -EINVAL;
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}
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}
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retval = of_address_to_resource(dn, 0, &res);
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if (retval) {
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dev_err(dev, "Error parsing memory region!\n");
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@ -680,11 +701,23 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
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return -EINVAL;
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}
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if (mdma->is_mpc8308) {
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retval = devm_request_irq(dev, mdma->irq2, &mpc_dma_irq, 0,
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DRV_NAME, mdma);
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if (retval) {
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dev_err(dev, "Error requesting IRQ2!\n");
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return -EINVAL;
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}
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}
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spin_lock_init(&mdma->error_status_lock);
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dma = &mdma->dma;
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dma->dev = dev;
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dma->chancnt = MPC_DMA_CHANNELS;
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if (!mdma->is_mpc8308)
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dma->chancnt = MPC_DMA_CHANNELS;
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else
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dma->chancnt = 16; /* MPC8308 DMA has only 16 channels */
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dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
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dma->device_free_chan_resources = mpc_dma_free_chan_resources;
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dma->device_issue_pending = mpc_dma_issue_pending;
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@ -720,26 +753,40 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
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* - Round-robin group arbitration,
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* - Round-robin channel arbitration.
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*/
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out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
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MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
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if (!mdma->is_mpc8308) {
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out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
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MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
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/* Disable hardware DMA requests */
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out_be32(&mdma->regs->dmaerqh, 0);
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out_be32(&mdma->regs->dmaerql, 0);
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/* Disable hardware DMA requests */
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out_be32(&mdma->regs->dmaerqh, 0);
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out_be32(&mdma->regs->dmaerql, 0);
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/* Disable error interrupts */
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out_be32(&mdma->regs->dmaeeih, 0);
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out_be32(&mdma->regs->dmaeeil, 0);
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/* Disable error interrupts */
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out_be32(&mdma->regs->dmaeeih, 0);
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out_be32(&mdma->regs->dmaeeil, 0);
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/* Clear interrupts status */
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out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
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/* Clear interrupts status */
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out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
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out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
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/* Route interrupts to IPIC */
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out_be32(&mdma->regs->dmaihsa, 0);
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out_be32(&mdma->regs->dmailsa, 0);
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/* Route interrupts to IPIC */
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out_be32(&mdma->regs->dmaihsa, 0);
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out_be32(&mdma->regs->dmailsa, 0);
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} else {
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/* MPC8308 has 16 channels and lacks some registers */
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out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA);
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/* enable snooping */
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out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE);
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/* Disable error interrupts */
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out_be32(&mdma->regs->dmaeeil, 0);
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/* Clear interrupts status */
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out_be32(&mdma->regs->dmaintl, 0xFFFF);
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out_be32(&mdma->regs->dmaerrl, 0xFFFF);
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}
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/* Register DMA engine */
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dev_set_drvdata(dev, mdma);
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