[POWERPC] Adapt ipic driver to new host_ops interface, add set_irq_type to set IRQ sense
This converts ipic code to Benh's IRQ mods. For the IPIC, IRQ sense values in the device tree equal those in include/linux/irq.h; that's 8 for low assertion (most internal IRQs on mpc83xx), and 2 for high-to-low change. spinlocks added to [un]mask, ack operations; default handler and type now set in host_map; and redundant condition check eliminated. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Kim Phillips
Paul Mackerras
parent
bf4152dd7c
commit
b9f0f1bb2b
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@ -19,15 +19,18 @@
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/sysdev.h>
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#include <linux/device.h>
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#include <linux/bootmem.h>
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#include <linux/spinlock.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/ipic.h>
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#include <asm/mpc83xx.h>
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#include "ipic.h"
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static struct ipic p_ipic;
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static struct ipic * primary_ipic;
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static DEFINE_SPINLOCK(ipic_lock);
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static struct ipic_info ipic_info[] = {
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[9] = {
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@ -373,74 +376,220 @@ static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32
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out_be32(base + (reg >> 2), value);
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}
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static inline struct ipic * ipic_from_irq(unsigned int irq)
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static inline struct ipic * ipic_from_irq(unsigned int virq)
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{
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return primary_ipic;
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}
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static void ipic_enable_irq(unsigned int irq)
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#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
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static void ipic_unmask_irq(unsigned int virq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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unsigned long flags;
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u32 temp;
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spin_lock_irqsave(&ipic_lock, flags);
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temp = ipic_read(ipic->regs, ipic_info[src].mask);
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temp |= (1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].mask, temp);
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spin_unlock_irqrestore(&ipic_lock, flags);
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}
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static void ipic_disable_irq(unsigned int irq)
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static void ipic_mask_irq(unsigned int virq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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unsigned long flags;
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u32 temp;
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spin_lock_irqsave(&ipic_lock, flags);
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temp = ipic_read(ipic->regs, ipic_info[src].mask);
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temp &= ~(1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].mask, temp);
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spin_unlock_irqrestore(&ipic_lock, flags);
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}
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static void ipic_disable_irq_and_ack(unsigned int irq)
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static void ipic_ack_irq(unsigned int virq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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unsigned long flags;
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u32 temp;
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ipic_disable_irq(irq);
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spin_lock_irqsave(&ipic_lock, flags);
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temp = ipic_read(ipic->regs, ipic_info[src].pend);
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temp |= (1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].pend, temp);
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spin_unlock_irqrestore(&ipic_lock, flags);
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}
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static void ipic_end_irq(unsigned int irq)
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static void ipic_mask_irq_and_ack(unsigned int virq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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ipic_enable_irq(irq);
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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unsigned long flags;
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u32 temp;
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spin_lock_irqsave(&ipic_lock, flags);
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temp = ipic_read(ipic->regs, ipic_info[src].mask);
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temp &= ~(1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].mask, temp);
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temp = ipic_read(ipic->regs, ipic_info[src].pend);
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temp |= (1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].pend, temp);
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spin_unlock_irqrestore(&ipic_lock, flags);
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}
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struct hw_interrupt_type ipic = {
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.typename = " IPIC ",
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.enable = ipic_enable_irq,
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.disable = ipic_disable_irq,
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.ack = ipic_disable_irq_and_ack,
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.end = ipic_end_irq,
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static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
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{
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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struct irq_desc *desc = get_irq_desc(virq);
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unsigned int vold, vnew, edibit;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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/* ipic supports only low assertion and high-to-low change senses
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*/
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if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
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printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
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flow_type);
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return -EINVAL;
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}
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desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
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desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
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if (flow_type & IRQ_TYPE_LEVEL_LOW) {
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desc->status |= IRQ_LEVEL;
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set_irq_handler(virq, handle_level_irq);
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} else {
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set_irq_handler(virq, handle_edge_irq);
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}
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/* only EXT IRQ senses are programmable on ipic
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* internal IRQ senses are LEVEL_LOW
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*/
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if (src == IPIC_IRQ_EXT0)
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edibit = 15;
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else
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if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
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edibit = (14 - (src - IPIC_IRQ_EXT1));
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else
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return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
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vold = ipic_read(ipic->regs, IPIC_SECNR);
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if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
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vnew = vold | (1 << edibit);
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} else {
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vnew = vold & ~(1 << edibit);
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}
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if (vold != vnew)
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ipic_write(ipic->regs, IPIC_SECNR, vnew);
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return 0;
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}
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static struct irq_chip ipic_irq_chip = {
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.typename = " IPIC ",
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.unmask = ipic_unmask_irq,
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.mask = ipic_mask_irq,
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.mask_ack = ipic_mask_irq_and_ack,
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.ack = ipic_ack_irq,
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.set_type = ipic_set_irq_type,
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};
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void __init ipic_init(phys_addr_t phys_addr,
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unsigned int flags,
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unsigned int irq_offset,
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unsigned char *senses,
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unsigned int senses_count)
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static int ipic_host_match(struct irq_host *h, struct device_node *node)
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{
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u32 i, temp = 0;
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struct ipic *ipic = h->host_data;
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primary_ipic = &p_ipic;
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primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
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/* Exact match, unless ipic node is NULL */
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return ipic->of_node == NULL || ipic->of_node == node;
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}
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primary_ipic->irq_offset = irq_offset;
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static int ipic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct ipic *ipic = h->host_data;
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struct irq_chip *chip;
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ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
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/* Default chip */
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chip = &ipic->hc_irq;
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set_irq_chip_data(virq, ipic);
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set_irq_chip_and_handler(virq, chip, handle_level_irq);
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/* interrupt sense values coming from the device tree equal either
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* LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
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*/
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*out_hwirq = intspec[0];
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if (intsize > 1)
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*out_flags = intspec[1];
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else
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static struct irq_host_ops ipic_host_ops = {
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.match = ipic_host_match,
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.map = ipic_host_map,
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.xlate = ipic_host_xlate,
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};
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void __init ipic_init(struct device_node *node,
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unsigned int flags)
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{
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struct ipic *ipic;
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struct resource res;
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u32 temp = 0, ret;
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ipic = alloc_bootmem(sizeof(struct ipic));
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if (ipic == NULL)
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return;
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memset(ipic, 0, sizeof(struct ipic));
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ipic->of_node = node ? of_node_get(node) : NULL;
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ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
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NR_IPIC_INTS,
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&ipic_host_ops, 0);
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if (ipic->irqhost == NULL) {
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of_node_put(node);
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return;
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}
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ret = of_address_to_resource(node, 0, &res);
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if (ret)
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return;
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ipic->regs = ioremap(res.start, res.end - res.start + 1);
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ipic->irqhost->host_data = ipic;
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ipic->hc_irq = ipic_irq_chip;
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/* init hw */
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ipic_write(ipic->regs, IPIC_SICNR, 0x0);
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/* default priority scheme is grouped. If spread mode is required
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* configure SICFR accordingly */
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@ -453,49 +602,35 @@ void __init ipic_init(phys_addr_t phys_addr,
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if (flags & IPIC_SPREADMODE_MIX_B)
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temp |= SICFR_MPSB;
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ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
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ipic_write(ipic->regs, IPIC_SICNR, temp);
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/* handle MCP route */
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temp = 0;
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if (flags & IPIC_DISABLE_MCP_OUT)
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temp = SERCR_MCPR;
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ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
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ipic_write(ipic->regs, IPIC_SERCR, temp);
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/* handle routing of IRQ0 to MCP */
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temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
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temp = ipic_read(ipic->regs, IPIC_SEMSR);
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if (flags & IPIC_IRQ0_MCP)
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temp |= SEMSR_SIRQ0;
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else
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temp &= ~SEMSR_SIRQ0;
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ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
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ipic_write(ipic->regs, IPIC_SEMSR, temp);
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for (i = 0 ; i < NR_IPIC_INTS ; i++) {
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irq_desc[i+irq_offset].chip = &ipic;
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irq_desc[i+irq_offset].status = IRQ_LEVEL;
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}
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primary_ipic = ipic;
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irq_set_default_host(primary_ipic->irqhost);
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temp = 0;
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for (i = 0 ; i < senses_count ; i++) {
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if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
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temp |= 1 << (15 - i);
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if (i != 0)
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irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
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else
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irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
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}
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}
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ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
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printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
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senses_count, primary_ipic->regs);
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printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
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primary_ipic->regs);
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}
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int ipic_set_priority(unsigned int irq, unsigned int priority)
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int ipic_set_priority(unsigned int virq, unsigned int priority)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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u32 temp;
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if (priority > 7)
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@ -520,10 +655,10 @@ int ipic_set_priority(unsigned int irq, unsigned int priority)
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return 0;
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}
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void ipic_set_highest_priority(unsigned int irq)
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void ipic_set_highest_priority(unsigned int virq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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struct ipic *ipic = ipic_from_irq(virq);
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unsigned int src = ipic_irq_to_hw(virq);
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u32 temp;
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temp = ipic_read(ipic->regs, IPIC_SICFR);
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@ -537,37 +672,10 @@ void ipic_set_highest_priority(unsigned int irq)
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void ipic_set_default_priority(void)
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{
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ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
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ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
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ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
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ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
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ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
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ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
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ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
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ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
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ipic_set_priority(MPC83xx_IRQ_UART1, 0);
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ipic_set_priority(MPC83xx_IRQ_UART2, 1);
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ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
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ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
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ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
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ipic_set_priority(MPC83xx_IRQ_SPI, 7);
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ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
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ipic_set_priority(MPC83xx_IRQ_PIT, 1);
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ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
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ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
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ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
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ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
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ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
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ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
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ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
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ipic_set_priority(MPC83xx_IRQ_MU, 1);
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ipic_set_priority(MPC83xx_IRQ_SBA, 2);
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ipic_set_priority(MPC83xx_IRQ_DMA, 3);
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ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
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ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
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ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
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ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
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ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
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ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
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}
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void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
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@ -600,17 +708,20 @@ void ipic_clear_mcp_status(u32 mask)
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ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
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}
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/* Return an interrupt vector or -1 if no interrupt is pending. */
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int ipic_get_irq(struct pt_regs *regs)
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int ipic_get_irq(struct pt_regs *regs)
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{
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int irq;
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irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
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BUG_ON(primary_ipic == NULL);
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#define IPIC_SIVCR_VECTOR_MASK 0x7f
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irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
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if (irq == 0) /* 0 --> no irq is pending */
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irq = -1;
|
||||
return NO_IRQ;
|
||||
|
||||
return irq;
|
||||
return irq_linear_revmap(primary_ipic->irqhost, irq);
|
||||
}
|
||||
|
||||
static struct sysdev_class ipic_sysclass = {
|
||||
|
|
|
|||
|
|
@ -15,7 +15,18 @@
|
|||
|
||||
#include <asm/ipic.h>
|
||||
|
||||
#define MPC83xx_IPIC_SIZE (0x00100)
|
||||
#define NR_IPIC_INTS 128
|
||||
|
||||
/* External IRQS */
|
||||
#define IPIC_IRQ_EXT0 48
|
||||
#define IPIC_IRQ_EXT1 17
|
||||
#define IPIC_IRQ_EXT7 23
|
||||
|
||||
/* Default Priority Registers */
|
||||
#define IPIC_SIPRR_A_DEFAULT 0x05309770
|
||||
#define IPIC_SIPRR_D_DEFAULT 0x05309770
|
||||
#define IPIC_SMPRR_A_DEFAULT 0x05309770
|
||||
#define IPIC_SMPRR_B_DEFAULT 0x05309770
|
||||
|
||||
/* System Global Interrupt Configuration Register */
|
||||
#define SICFR_IPSA 0x00010000
|
||||
|
|
@ -31,7 +42,15 @@
|
|||
|
||||
struct ipic {
|
||||
volatile u32 __iomem *regs;
|
||||
unsigned int irq_offset;
|
||||
|
||||
/* The remapper for this IPIC */
|
||||
struct irq_host *irqhost;
|
||||
|
||||
/* The "linux" controller struct */
|
||||
struct irq_chip hc_irq;
|
||||
|
||||
/* The device node of the interrupt controller */
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
struct ipic_info {
|
||||
|
|
|
|||
Reference in New Issue