ASoC: ad193x: Use snd_soc_update_bits where appropriate
We can reduce the code size here a bit by using snd_soc_update_bits instead of open-coding the read-modify-write cycle. The conversion done in this patch is not completely straightforward and some minor code restructuring has been incorporated to further reduce the code size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Lars-Peter Clausen
Mark Brown
parent
0718fd2777
commit
b82ca578fd
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@ -123,35 +123,29 @@ static int ad193x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
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unsigned int rx_mask, int slots, int width)
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{
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struct snd_soc_codec *codec = dai->codec;
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int dac_reg = snd_soc_read(codec, AD193X_DAC_CTRL1);
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int adc_reg = snd_soc_read(codec, AD193X_ADC_CTRL2);
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dac_reg &= ~AD193X_DAC_CHAN_MASK;
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adc_reg &= ~AD193X_ADC_CHAN_MASK;
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unsigned int channels;
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switch (slots) {
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case 2:
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dac_reg |= AD193X_DAC_2_CHANNELS << AD193X_DAC_CHAN_SHFT;
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adc_reg |= AD193X_ADC_2_CHANNELS << AD193X_ADC_CHAN_SHFT;
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channels = AD193X_2_CHANNELS;
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break;
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case 4:
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dac_reg |= AD193X_DAC_4_CHANNELS << AD193X_DAC_CHAN_SHFT;
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adc_reg |= AD193X_ADC_4_CHANNELS << AD193X_ADC_CHAN_SHFT;
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channels = AD193X_4_CHANNELS;
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break;
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case 8:
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dac_reg |= AD193X_DAC_8_CHANNELS << AD193X_DAC_CHAN_SHFT;
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adc_reg |= AD193X_ADC_8_CHANNELS << AD193X_ADC_CHAN_SHFT;
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channels = AD193X_8_CHANNELS;
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break;
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case 16:
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dac_reg |= AD193X_DAC_16_CHANNELS << AD193X_DAC_CHAN_SHFT;
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adc_reg |= AD193X_ADC_16_CHANNELS << AD193X_ADC_CHAN_SHFT;
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channels = AD193X_16_CHANNELS;
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break;
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default:
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return -EINVAL;
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}
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snd_soc_write(codec, AD193X_DAC_CTRL1, dac_reg);
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snd_soc_write(codec, AD193X_ADC_CTRL2, adc_reg);
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snd_soc_update_bits(codec, AD193X_DAC_CTRL1, AD193X_DAC_CHAN_MASK,
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channels << AD193X_DAC_CHAN_SHFT);
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snd_soc_update_bits(codec, AD193X_ADC_CTRL2, AD193X_ADC_CHAN_MASK,
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channels << AD193X_ADC_CHAN_SHFT);
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return 0;
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}
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@ -160,23 +154,19 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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int adc_reg1, adc_reg2, dac_reg;
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adc_reg1 = snd_soc_read(codec, AD193X_ADC_CTRL1);
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adc_reg2 = snd_soc_read(codec, AD193X_ADC_CTRL2);
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dac_reg = snd_soc_read(codec, AD193X_DAC_CTRL1);
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unsigned int adc_serfmt = 0;
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unsigned int adc_fmt = 0;
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unsigned int dac_fmt = 0;
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/* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S
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* with TDM) and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A)
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*/
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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adc_reg1 &= ~AD193X_ADC_SERFMT_MASK;
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adc_reg1 |= AD193X_ADC_SERFMT_TDM;
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adc_serfmt |= AD193X_ADC_SERFMT_TDM;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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adc_reg1 &= ~AD193X_ADC_SERFMT_MASK;
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adc_reg1 |= AD193X_ADC_SERFMT_AUX;
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adc_serfmt |= AD193X_ADC_SERFMT_AUX;
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break;
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default:
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return -EINVAL;
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@ -184,29 +174,20 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
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adc_reg2 &= ~AD193X_ADC_LEFT_HIGH;
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adc_reg2 &= ~AD193X_ADC_BCLK_INV;
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dac_reg &= ~AD193X_DAC_LEFT_HIGH;
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dac_reg &= ~AD193X_DAC_BCLK_INV;
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break;
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case SND_SOC_DAIFMT_NB_IF: /* normal bclk + invert frm */
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adc_reg2 |= AD193X_ADC_LEFT_HIGH;
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adc_reg2 &= ~AD193X_ADC_BCLK_INV;
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dac_reg |= AD193X_DAC_LEFT_HIGH;
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dac_reg &= ~AD193X_DAC_BCLK_INV;
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adc_fmt |= AD193X_ADC_LEFT_HIGH;
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dac_fmt |= AD193X_DAC_LEFT_HIGH;
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break;
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case SND_SOC_DAIFMT_IB_NF: /* invert bclk + normal frm */
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adc_reg2 &= ~AD193X_ADC_LEFT_HIGH;
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adc_reg2 |= AD193X_ADC_BCLK_INV;
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dac_reg &= ~AD193X_DAC_LEFT_HIGH;
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dac_reg |= AD193X_DAC_BCLK_INV;
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adc_fmt |= AD193X_ADC_BCLK_INV;
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dac_fmt |= AD193X_DAC_BCLK_INV;
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break;
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case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */
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adc_reg2 |= AD193X_ADC_LEFT_HIGH;
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adc_reg2 |= AD193X_ADC_BCLK_INV;
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dac_reg |= AD193X_DAC_LEFT_HIGH;
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dac_reg |= AD193X_DAC_BCLK_INV;
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adc_fmt |= AD193X_ADC_LEFT_HIGH;
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adc_fmt |= AD193X_ADC_BCLK_INV;
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dac_fmt |= AD193X_DAC_LEFT_HIGH;
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dac_fmt |= AD193X_DAC_BCLK_INV;
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break;
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default:
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return -EINVAL;
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@ -214,36 +195,31 @@ static int ad193x_set_dai_fmt(struct snd_soc_dai *codec_dai,
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */
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adc_reg2 |= AD193X_ADC_LCR_MASTER;
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adc_reg2 |= AD193X_ADC_BCLK_MASTER;
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dac_reg |= AD193X_DAC_LCR_MASTER;
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dac_reg |= AD193X_DAC_BCLK_MASTER;
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adc_fmt |= AD193X_ADC_LCR_MASTER;
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adc_fmt |= AD193X_ADC_BCLK_MASTER;
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dac_fmt |= AD193X_DAC_LCR_MASTER;
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dac_fmt |= AD193X_DAC_BCLK_MASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & frm master */
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adc_reg2 |= AD193X_ADC_LCR_MASTER;
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adc_reg2 &= ~AD193X_ADC_BCLK_MASTER;
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dac_reg |= AD193X_DAC_LCR_MASTER;
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dac_reg &= ~AD193X_DAC_BCLK_MASTER;
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adc_fmt |= AD193X_ADC_LCR_MASTER;
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dac_fmt |= AD193X_DAC_LCR_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
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adc_reg2 &= ~AD193X_ADC_LCR_MASTER;
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adc_reg2 |= AD193X_ADC_BCLK_MASTER;
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dac_reg &= ~AD193X_DAC_LCR_MASTER;
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dac_reg |= AD193X_DAC_BCLK_MASTER;
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adc_fmt |= AD193X_ADC_BCLK_MASTER;
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dac_fmt |= AD193X_DAC_BCLK_MASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */
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adc_reg2 &= ~AD193X_ADC_LCR_MASTER;
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adc_reg2 &= ~AD193X_ADC_BCLK_MASTER;
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dac_reg &= ~AD193X_DAC_LCR_MASTER;
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dac_reg &= ~AD193X_DAC_BCLK_MASTER;
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break;
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default:
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return -EINVAL;
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}
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snd_soc_write(codec, AD193X_ADC_CTRL1, adc_reg1);
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snd_soc_write(codec, AD193X_ADC_CTRL2, adc_reg2);
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snd_soc_write(codec, AD193X_DAC_CTRL1, dac_reg);
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snd_soc_update_bits(codec, AD193X_ADC_CTRL1, AD193X_ADC_SERFMT_MASK,
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adc_serfmt);
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snd_soc_update_bits(codec, AD193X_ADC_CTRL2, AD193X_ADC_FMT_MASK,
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adc_fmt);
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snd_soc_update_bits(codec, AD193X_DAC_CTRL1, AD193X_DAC_FMT_MASK,
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dac_fmt);
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return 0;
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}
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@ -23,16 +23,14 @@
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#define AD193X_DAC_SERFMT_STEREO (0 << 6)
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#define AD193X_DAC_SERFMT_TDM (1 << 6)
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#define AD193X_DAC_CTRL1 0x03
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#define AD193X_DAC_2_CHANNELS 0
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#define AD193X_DAC_4_CHANNELS 1
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#define AD193X_DAC_8_CHANNELS 2
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#define AD193X_DAC_16_CHANNELS 3
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#define AD193X_DAC_CHAN_SHFT 1
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#define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT)
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#define AD193X_DAC_LCR_MASTER (1 << 4)
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#define AD193X_DAC_BCLK_MASTER (1 << 5)
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#define AD193X_DAC_LEFT_HIGH (1 << 3)
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#define AD193X_DAC_BCLK_INV (1 << 7)
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#define AD193X_DAC_FMT_MASK (AD193X_DAC_LCR_MASTER | \
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AD193X_DAC_BCLK_MASTER | AD193X_DAC_LEFT_HIGH | AD193X_DAC_BCLK_INV)
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#define AD193X_DAC_CTRL2 0x04
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#define AD193X_DAC_WORD_LEN_SHFT 3
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#define AD193X_DAC_WORD_LEN_MASK 0x18
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@ -68,16 +66,19 @@
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#define AD193X_ADC_SERFMT_AUX (2 << 5)
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#define AD193X_ADC_WORD_LEN_MASK 0x3
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#define AD193X_ADC_CTRL2 0x10
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#define AD193X_ADC_2_CHANNELS 0
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#define AD193X_ADC_4_CHANNELS 1
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#define AD193X_ADC_8_CHANNELS 2
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#define AD193X_ADC_16_CHANNELS 3
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#define AD193X_ADC_CHAN_SHFT 4
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#define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT)
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#define AD193X_ADC_LCR_MASTER (1 << 3)
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#define AD193X_ADC_BCLK_MASTER (1 << 6)
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#define AD193X_ADC_LEFT_HIGH (1 << 2)
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#define AD193X_ADC_BCLK_INV (1 << 1)
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#define AD193X_ADC_FMT_MASK (AD193X_ADC_LCR_MASTER | \
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AD193X_ADC_BCLK_MASTER | AD193X_ADC_LEFT_HIGH | AD193X_ADC_BCLK_INV)
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#define AD193X_2_CHANNELS 0
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#define AD193X_4_CHANNELS 1
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#define AD193X_8_CHANNELS 2
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#define AD193X_16_CHANNELS 3
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#define AD193X_NUM_REGS 17
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