gma500: Fix Cedarview support (Correct version)
And update to the actual product naming as the press release is now out. http://newsroom.intel.com/docs/DOC-2553#pressmaterials - Fixes the wrong ifdef check - Fixes the missing crtc count declaration Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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4 changed files with 8 additions and 6 deletions
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@ -19,8 +19,9 @@ config DRM_GMA600
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platforms with LVDS ports. HDMI and MIPI are not currently
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supported.
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config DRM_CEDARVIEW
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bool "Intel Cedarview support (Experimental)"
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config DRM_GMA3600
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bool "Intel GMA3600/3650 support (Experimental)"
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depends on DRM_GMA500
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help
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Say yes to include support for Intel Cedarview platforms
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Say yes to include basic support for Intel GMA3600/3650 (Intel
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Cedar Trail) platforms.
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@ -25,7 +25,7 @@ gma500_gfx-y += gem_glue.o \
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psb_device.o \
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mid_bios.o
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gma500_gfx-$(CONFIG_DRM_CEDARVIEW) += cdv_device.o \
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gma500_gfx-$(CONFIG_DRM_GMA3600) += cdv_device.o \
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cdv_intel_crt.o \
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cdv_intel_display.o \
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cdv_intel_hdmi.o \
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@ -327,9 +327,10 @@ static int cdv_chip_setup(struct drm_device *dev)
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/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
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const struct psb_ops cdv_chip_ops = {
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.name = "Cedartrail",
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.name = "GMA3600/3650",
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.accel_2d = 0,
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.pipes = 2,
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.crtcs = 2,
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.sgx_offset = MRST_SGX_OFFSET,
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.chip_setup = cdv_chip_setup,
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@ -64,7 +64,7 @@ static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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/* Atom E620 */
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{ 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
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#endif
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#if defined(CONFIG_DRM_CDV)
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#if defined(CONFIG_DRM_GMA3600)
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{ 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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{ 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
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