microblaze: Change register usage for ESR and EAR
This change synchronize register usage in code. ESR = R4 EAR = R3 Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
7a6bbdc930
commit
b175bcfe31
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@ -313,13 +313,13 @@ _hw_exception_handler:
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mfs r5, rmsr;
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nop
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swi r5, r1, 0;
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mfs r3, resr
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mfs r4, resr
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nop
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mfs r4, rear;
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mfs r3, rear;
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nop
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#ifndef CONFIG_MMU
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andi r5, r3, 0x1000; /* Check ESR[DS] */
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andi r5, r4, 0x1000; /* Check ESR[DS] */
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beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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@ -327,7 +327,7 @@ not_in_delay_slot:
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swi r17, r1, PT_R17
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#endif
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andi r5, r3, 0x1F; /* Extract ESR[EXC] */
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andi r5, r4, 0x1F; /* Extract ESR[EXC] */
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#ifdef CONFIG_MMU
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/* Calculate exception vector offset = r5 << 2 */
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@ -378,7 +378,7 @@ handle_other_ex: /* Handle Other exceptions here */
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swi r18, r1, PT_R18
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or r5, r1, r0
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andi r6, r3, 0x1F; /* Load ESR[EC] */
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andi r6, r4, 0x1F; /* Load ESR[EC] */
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lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
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swi r7, r1, PT_MODE
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mfs r7, rfsr
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@ -428,11 +428,11 @@ handle_other_ex: /* Handle Other exceptions here */
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*/
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handle_unaligned_ex:
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/* Working registers already saved: R3, R4, R5, R6
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* R3 = ESR
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* R4 = EAR
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* R4 = ESR
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* R3 = EAR
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*/
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#ifdef CONFIG_MMU
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andi r6, r3, 0x1000 /* Check ESR[DS] */
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andi r6, r4, 0x1000 /* Check ESR[DS] */
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beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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@ -441,7 +441,7 @@ _no_delayslot:
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RESTORE_STATE;
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bri unaligned_data_trap
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#endif
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andi r6, r3, 0x3E0; /* Mask and extract the register operand */
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andi r6, r4, 0x3E0; /* Mask and extract the register operand */
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srl r6, r6; /* r6 >> 5 */
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srl r6, r6;
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srl r6, r6;
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@ -450,33 +450,33 @@ _no_delayslot:
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/* Store the register operand in a temporary location */
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sbi r6, r0, TOPHYS(ex_reg_op);
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andi r6, r3, 0x400; /* Extract ESR[S] */
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andi r6, r4, 0x400; /* Extract ESR[S] */
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bnei r6, ex_sw;
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ex_lw:
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andi r6, r3, 0x800; /* Extract ESR[W] */
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andi r6, r4, 0x800; /* Extract ESR[W] */
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beqi r6, ex_lhw;
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lbui r5, r4, 0; /* Exception address in r4 */
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lbui r5, r3, 0; /* Exception address in r3 */
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/* Load a word, byte-by-byte from destination address
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and save it in tmp space */
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r5, r4, 1;
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lbui r5, r3, 1;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
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lbui r5, r4, 2;
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lbui r5, r3, 2;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
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lbui r5, r4, 3;
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lbui r5, r3, 3;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
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/* Get the destination register value into r3 */
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lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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/* Get the destination register value into r4 */
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lwi r4, r0, TOPHYS(ex_tmp_data_loc_0);
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bri ex_lw_tail;
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ex_lhw:
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lbui r5, r4, 0; /* Exception address in r4 */
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lbui r5, r3, 0; /* Exception address in r3 */
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/* Load a half-word, byte-by-byte from destination
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address and save it in tmp space */
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r5, r4, 1;
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lbui r5, r3, 1;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
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/* Get the destination register value into r3 */
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lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
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/* Get the destination register value into r4 */
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lhui r4, r0, TOPHYS(ex_tmp_data_loc_0);
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ex_lw_tail:
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/* Get the destination register number into r5 */
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lbui r5, r0, TOPHYS(ex_reg_op);
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@ -504,25 +504,25 @@ ex_sw_tail:
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andi r6, r6, 0x800; /* Extract ESR[W] */
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beqi r6, ex_shw;
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/* Get the word - delay slot */
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swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
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/* Store the word, byte-by-byte into destination address */
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
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sbi r3, r4, 0;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
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sbi r3, r4, 1;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r3, r4, 2;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r3, r4, 3;
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_0);
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sbi r4, r3, 0;
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_1);
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sbi r4, r3, 1;
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r4, r3, 2;
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r4, r3, 3;
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bri ex_handler_done;
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ex_shw:
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/* Store the lower half-word, byte-by-byte into destination address */
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swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r3, r4, 0;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r3, r4, 1;
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swi r4, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r4, r3, 0;
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lbui r4, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r4, r3, 1;
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ex_sw_end: /* Exception handling of store word, ends. */
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ex_handler_done:
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