OMAPDSS: DISPC: cleanup lcd/digit enable/disable
We currently have a single function to enable and disable the manager output for LCD and DIGIT. The functions are a bit complex, as handling both enable and disable require some extra steps to ensure that the output is enabled or disabled properly without errors before exiting the function. The code can be made simpler to understand by splitting the functions into separate enable and disable functions. We'll also clean up the comments and some parameter names at the same time. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
parent
cb699200af
commit
b111224900
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@ -772,7 +772,7 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
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if (!dss_data.irq_enabled && need_isr())
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dss_register_vsync_isr();
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dispc_mgr_enable(mgr->id, true);
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dispc_mgr_enable(mgr->id);
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mgr_clear_shadow_dirty(mgr);
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@ -1027,7 +1027,7 @@ int dss_mgr_enable(struct omap_overlay_manager *mgr)
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spin_unlock_irqrestore(&data_lock, flags);
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if (!mgr_manual_update(mgr))
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dispc_mgr_enable(mgr->id, true);
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dispc_mgr_enable(mgr->id);
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out:
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mutex_unlock(&apply_lock);
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@ -1052,7 +1052,7 @@ void dss_mgr_disable(struct omap_overlay_manager *mgr)
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goto out;
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if (!mgr_manual_update(mgr))
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dispc_mgr_enable(mgr->id, false);
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dispc_mgr_disable(mgr->id);
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spin_lock_irqsave(&data_lock, flags);
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@ -2589,7 +2589,7 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable)
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return 0;
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}
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static void dispc_disable_isr(void *data, u32 mask)
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static void dispc_mgr_disable_isr(void *data, u32 mask)
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{
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struct completion *compl = data;
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complete(compl);
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@ -2607,122 +2607,172 @@ bool dispc_mgr_is_enabled(enum omap_channel channel)
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return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
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}
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static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
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static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
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{
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struct completion frame_done_completion;
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bool is_on;
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_enable_mgr_out(channel, true);
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}
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static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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int r;
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u32 irq;
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/* When we disable LCD output, we need to wait until frame is done.
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* Otherwise the DSS is still working, and turning off the clocks
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* prevents DSS from going to OFF mode */
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is_on = dispc_mgr_is_enabled(channel);
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if (dispc_mgr_is_enabled(channel) == false)
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return;
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irq = mgr_desc[channel].framedone_irq;
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/*
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* When we disable LCD output, we need to wait for FRAMEDONE to know
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* that DISPC has finished with the LCD output.
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*/
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if (!enable && is_on) {
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init_completion(&frame_done_completion);
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irq = dispc_mgr_get_framedone_irq(channel);
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r = omap_dispc_register_isr(dispc_disable_isr,
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&frame_done_completion, irq);
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to register FRAMEDONE isr\n");
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if (r)
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DSSERR("failed to register FRAMEDONE isr\n");
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_enable_mgr_out(channel, false);
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/* if we couldn't register for framedone, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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_enable_mgr_out(channel, enable);
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for FRAME DONE\n");
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if (!enable && is_on) {
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if (!wait_for_completion_timeout(&frame_done_completion,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for FRAME DONE\n");
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r = omap_dispc_unregister_isr(dispc_disable_isr,
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&frame_done_completion, irq);
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if (r)
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DSSERR("failed to unregister FRAMEDONE isr\n");
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}
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq);
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if (r)
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DSSERR("failed to unregister FRAMEDONE isr\n");
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}
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static void dispc_mgr_enable_digit_out(bool enable)
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static void dispc_digit_out_enable_isr(void *data, u32 mask)
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{
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struct completion frame_done_completion;
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struct completion *compl = data;
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/* ignore any sync lost interrupts */
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if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
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complete(compl);
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}
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static void dispc_mgr_enable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(vsync_compl);
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int r;
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u32 irq_mask;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
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return;
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/*
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* Digit output produces some sync lost interrupts during the first
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* frame when enabling. Those need to be ignored, so we register for the
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* sync lost irq to prevent the error handler from triggering.
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*/
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
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dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
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r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r) {
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DSSERR("failed to register %x isr\n", irq_mask);
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return;
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}
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_enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, true);
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/* wait for the first evsync */
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if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to start\n");
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r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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}
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static void dispc_mgr_disable_digit_out(void)
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{
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DECLARE_COMPLETION_ONSTACK(framedone_compl);
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enum dss_hdmi_venc_clk_source_select src;
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int r, i;
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u32 irq_mask;
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int num_irqs;
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == enable)
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if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
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return;
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src = dss_get_hdmi_venc_clk_source();
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if (enable) {
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unsigned long flags;
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/* When we enable digit output, we'll get an extra digit
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* sync lost interrupt, that we need to ignore */
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spin_lock_irqsave(&dispc.irq_lock, flags);
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dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
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_omap_dispc_set_irqs();
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spin_unlock_irqrestore(&dispc.irq_lock, flags);
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}
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/*
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* When we disable the digit output, we need to wait for FRAMEDONE to
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* know that DISPC has finished with the output. For analog tv out we'll
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* use vsync, as omap2/3 don't have framedone for TV.
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*/
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/* When we disable digit output, we need to wait until fields are done.
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* Otherwise the DSS is still working, and turning off the clocks
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* prevents DSS from going to OFF mode. And when enabling, we need to
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* wait for the extra sync losts */
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init_completion(&frame_done_completion);
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if (src == DSS_HDMI_M_PCLK && enable == false) {
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if (src == DSS_HDMI_M_PCLK) {
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irq_mask = DISPC_IRQ_FRAMEDONETV;
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num_irqs = 1;
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} else {
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irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
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/* XXX I understand from TRM that we should only wait for the
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* current field to complete. But it seems we have to wait for
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* both fields */
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irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
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/*
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* We need to wait for both even and odd vsyncs. Note that this
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* is not totally reliable, as we could get a vsync interrupt
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* before we disable the output, which leads to timeout in the
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* wait_for_completion.
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*/
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num_irqs = 2;
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}
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r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
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r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to register %x isr\n", irq_mask);
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_enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, enable);
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_enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, false);
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for (i = 0; i < num_irqs; ++i) {
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if (!wait_for_completion_timeout(&frame_done_completion,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to %s\n",
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enable ? "start" : "stop");
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/* if we couldn't register the irq, just sleep and exit */
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if (r) {
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msleep(100);
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return;
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}
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r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
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for (i = 0; i < num_irqs; ++i) {
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if (!wait_for_completion_timeout(&framedone_compl,
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for digit out to stop\n");
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}
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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irq_mask);
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if (r)
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DSSERR("failed to unregister %x isr\n", irq_mask);
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if (enable) {
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unsigned long flags;
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spin_lock_irqsave(&dispc.irq_lock, flags);
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dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
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dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
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_omap_dispc_set_irqs();
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spin_unlock_irqrestore(&dispc.irq_lock, flags);
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}
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}
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void dispc_mgr_enable(enum omap_channel channel, bool enable)
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void dispc_mgr_enable(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_enable_lcd_out(channel, enable);
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dispc_mgr_enable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_enable_digit_out(enable);
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dispc_mgr_enable_digit_out();
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else
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BUG();
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WARN_ON(1);
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}
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void dispc_mgr_disable(enum omap_channel channel)
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{
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if (dss_mgr_is_lcd(channel))
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dispc_mgr_disable_lcd_out(channel);
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else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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dispc_mgr_disable_digit_out();
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else
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WARN_ON(1);
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}
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void dispc_wb_enable(bool enable)
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@ -2739,7 +2789,7 @@ void dispc_wb_enable(bool enable)
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if (!enable && is_on) {
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init_completion(&frame_done_completion);
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r = omap_dispc_register_isr(dispc_disable_isr,
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r = omap_dispc_register_isr(dispc_mgr_disable_isr,
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&frame_done_completion, irq);
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if (r)
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DSSERR("failed to register FRAMEDONEWB isr\n");
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@ -2752,7 +2802,7 @@ void dispc_wb_enable(bool enable)
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msecs_to_jiffies(100)))
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DSSERR("timeout waiting for FRAMEDONEWB\n");
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r = omap_dispc_unregister_isr(dispc_disable_isr,
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r = omap_dispc_unregister_isr(dispc_mgr_disable_isr,
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&frame_done_completion, irq);
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if (r)
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DSSERR("failed to unregister FRAMEDONEWB isr\n");
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@ -438,7 +438,8 @@ u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
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bool dispc_mgr_go_busy(enum omap_channel channel);
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void dispc_mgr_go(enum omap_channel channel);
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bool dispc_mgr_is_enabled(enum omap_channel channel);
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void dispc_mgr_enable(enum omap_channel channel, bool enable);
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void dispc_mgr_enable(enum omap_channel channel);
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void dispc_mgr_disable(enum omap_channel channel);
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bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
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void dispc_mgr_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config);
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