USB: EHCI: Add MSM Host Controller driver
This patch adds support for EHCI compliant HSUSB Host controller found on MSM chips. The root hub has a single port and TT is built into it. This driver depends on OTG driver for PHY initialization, clock management and powering up VBUS. Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Pavankumar Kondeti
Greg Kroah-Hartman
parent
e0c201f339
commit
b0848aea10
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@ -64,6 +64,7 @@ config USB_ARCH_HAS_EHCI
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default y if ARCH_OMAP3
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default y if ARCH_VT8500
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default y if PLAT_SPEAR
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default y if ARCH_MSM
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default PCI
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# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
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@ -141,6 +141,17 @@ config USB_EHCI_HCD_OMAP
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Enables support for the on-chip EHCI controller on
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OMAP3 and later chips.
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config USB_EHCI_MSM
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bool "Support for MSM on-chip EHCI USB controller"
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depends on USB_EHCI_HCD && ARCH_MSM
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select USB_EHCI_ROOT_HUB_TT
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select USB_MSM_OTG_72K
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---help---
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Enables support for the USB Host controller present on the
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Qualcomm chipsets. Root Hub has inbuilt TT.
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This driver depends on OTG driver for PHY initialization,
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clock management, powering up VBUS.
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config USB_EHCI_HCD_PPC_OF
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bool "EHCI support for PPC USB controller on OF platform bus"
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depends on USB_EHCI_HCD && PPC_OF
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@ -1239,6 +1239,11 @@ MODULE_LICENSE ("GPL");
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#define PLATFORM_DRIVER spear_ehci_hcd_driver
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#endif
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#ifdef CONFIG_USB_EHCI_MSM
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#include "ehci-msm.c"
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#define PLATFORM_DRIVER ehci_msm_driver
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#endif
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#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
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!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
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!defined(XILINX_OF_PLATFORM_DRIVER)
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@ -0,0 +1,290 @@
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/* ehci-msm.c - HSUSB Host Controller Driver Implementation
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*
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* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
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*
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* Partly derived from ehci-fsl.c and ehci-hcd.c
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* Copyright (c) 2000-2004 by David Brownell
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* Copyright (c) 2005 MontaVista Software
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*
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* All source code in this file is licensed under the following license except
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* where indicated.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can find it at http://www.fsf.org
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*/
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/msm_hsusb_hw.h>
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#define MSM_USB_BASE (hcd->regs)
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static struct otg_transceiver *otg;
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/*
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* ehci_run defined in drivers/usb/host/ehci-hcd.c reset the controller and
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* the configuration settings in ehci_msm_reset vanish after controller is
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* reset. Resetting the controler in ehci_run seems to be un-necessary
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* provided HCD reset the controller before calling ehci_run. Most of the HCD
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* do but some are not. So this function is same as ehci_run but we don't
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* reset the controller here.
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*/
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static int ehci_msm_run(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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u32 temp;
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u32 hcc_params;
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hcd->uses_new_polling = 1;
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ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
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ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
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/*
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* hcc_params controls whether ehci->regs->segment must (!!!)
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* be used; it constrains QH/ITD/SITD and QTD locations.
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* pci_pool consistent memory always uses segment zero.
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* streaming mappings for I/O buffers, like pci_map_single(),
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* can return segments above 4GB, if the device allows.
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*
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* NOTE: the dma mask is visible through dma_supported(), so
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* drivers can pass this info along ... like NETIF_F_HIGHDMA,
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* Scsi_Host.highmem_io, and so forth. It's readonly to all
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* host side drivers though.
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*/
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hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
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if (HCC_64BIT_ADDR(hcc_params))
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ehci_writel(ehci, 0, &ehci->regs->segment);
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/*
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* Philips, Intel, and maybe others need CMD_RUN before the
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* root hub will detect new devices (why?); NEC doesn't
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*/
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ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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ehci->command |= CMD_RUN;
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ehci_writel(ehci, ehci->command, &ehci->regs->command);
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dbg_cmd(ehci, "init", ehci->command);
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/*
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* Start, enabling full USB 2.0 functionality ... usb 1.1 devices
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* are explicitly handed to companion controller(s), so no TT is
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* involved with the root hub. (Except where one is integrated,
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* and there's no companion controller unless maybe for USB OTG.)
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*
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* Turning on the CF flag will transfer ownership of all ports
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* from the companions to the EHCI controller. If any of the
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* companions are in the middle of a port reset at the time, it
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* could cause trouble. Write-locking ehci_cf_port_reset_rwsem
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* guarantees that no resets are in progress. After we set CF,
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* a short delay lets the hardware catch up; new resets shouldn't
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* be started before the port switching actions could complete.
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*/
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down_write(&ehci_cf_port_reset_rwsem);
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hcd->state = HC_STATE_RUNNING;
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ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
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ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
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usleep_range(5000, 5500);
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up_write(&ehci_cf_port_reset_rwsem);
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ehci->last_periodic_enable = ktime_get_real();
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temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
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ehci_info(ehci,
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"USB %x.%x started, EHCI %x.%02x%s\n",
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((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
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temp >> 8, temp & 0xff,
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ignore_oc ? ", overcurrent ignored" : "");
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ehci_writel(ehci, INTR_MASK,
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&ehci->regs->intr_enable); /* Turn On Interrupts */
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/* GRR this is run-once init(), being done every time the HC starts.
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* So long as they're part of class devices, we can't do it init()
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* since the class device isn't created that early.
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*/
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create_debug_files(ehci);
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create_companion_file(ehci);
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return 0;
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}
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static int ehci_msm_reset(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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int retval;
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ehci->caps = USB_CAPLENGTH;
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ehci->regs = USB_CAPLENGTH +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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/* cache the data to minimize the chip reads*/
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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hcd->has_tt = 1;
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ehci->sbrn = HCD_USB2;
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/* data structure init */
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retval = ehci_init(hcd);
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if (retval)
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return retval;
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retval = ehci_reset(ehci);
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if (retval)
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return retval;
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/* bursts of unspecified length. */
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writel(0, USB_AHBBURST);
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/* Use the AHB transactor */
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writel(0, USB_AHBMODE);
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/* Disable streaming mode and select host mode */
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writel(0x13, USB_USBMODE);
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ehci_port_power(ehci, 1);
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return 0;
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}
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static struct hc_driver msm_hc_driver = {
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.description = hcd_name,
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.product_desc = "Qualcomm On-Chip EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ehci_irq,
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.flags = HCD_USB2 | HCD_MEMORY,
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.reset = ehci_msm_reset,
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.start = ehci_msm_run,
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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/*
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* scheduling support
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*/
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.get_frame_number = ehci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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/*
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* PM support
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*/
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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};
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static int ehci_msm_probe(struct platform_device *pdev)
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{
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struct usb_hcd *hcd;
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struct resource *res;
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int ret;
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dev_dbg(&pdev->dev, "ehci_msm proble\n");
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hcd = usb_create_hcd(&msm_hc_driver, &pdev->dev, dev_name(&pdev->dev));
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if (!hcd) {
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dev_err(&pdev->dev, "Unable to create HCD\n");
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return -ENOMEM;
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}
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hcd->irq = platform_get_irq(pdev, 0);
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if (hcd->irq < 0) {
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dev_err(&pdev->dev, "Unable to get IRQ resource\n");
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ret = hcd->irq;
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goto put_hcd;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "Unable to get memory resource\n");
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ret = -ENODEV;
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goto put_hcd;
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}
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hcd->rsrc_start = res->start;
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hcd->rsrc_len = resource_size(res);
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hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
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if (!hcd->regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto put_hcd;
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}
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/*
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* OTG driver takes care of PHY initialization, clock management,
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* powering up VBUS and mapping of registers address space.
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*/
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otg = otg_get_transceiver();
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if (!otg) {
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dev_err(&pdev->dev, "unable to find transceiver\n");
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ret = -ENODEV;
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goto unmap;
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}
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ret = otg_set_host(otg, &hcd->self);
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if (ret < 0) {
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dev_err(&pdev->dev, "unable to register with transceiver\n");
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goto put_transceiver;
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}
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device_init_wakeup(&pdev->dev, 1);
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return 0;
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put_transceiver:
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otg_put_transceiver(otg);
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unmap:
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iounmap(hcd->regs);
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put_hcd:
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usb_put_hcd(hcd);
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return ret;
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}
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static int __devexit ehci_msm_remove(struct platform_device *pdev)
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{
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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device_init_wakeup(&pdev->dev, 0);
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otg_set_host(otg, NULL);
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otg_put_transceiver(otg);
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usb_put_hcd(hcd);
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return 0;
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}
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static struct platform_driver ehci_msm_driver = {
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.probe = ehci_msm_probe,
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.remove = __devexit_p(ehci_msm_remove),
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.driver = {
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.name = "msm_hsusb_host",
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},
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};
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