irqchip: sunxi: Add irq controller driver
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> CC: Thomas Gleixner <tglx@linutronix.de>
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Maxime Ripard
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afd24e1468
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Allwinner Sunxi Interrupt Controller
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Required properties:
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- compatible : should be "allwinner,sunxi-ic"
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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The interrupt sources are as follows:
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0: ENMI
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1: UART0
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2: UART1
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3: UART2
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4: UART3
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5: IR0
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6: IR1
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7: I2C0
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8: I2C1
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9: I2C2
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10: SPI0
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11: SPI1
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12: SPI2
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13: SPDIF
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14: AC97
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15: TS
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16: I2S
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17: UART4
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18: UART5
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19: UART6
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20: UART7
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21: KEYPAD
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22: TIMER0
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23: TIMER1
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24: TIMER2
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25: TIMER3
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26: CAN
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27: DMA
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28: PIO
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29: TOUCH_PANEL
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30: AUDIO_CODEC
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31: LRADC
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32: SDMC0
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33: SDMC1
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34: SDMC2
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35: SDMC3
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36: MEMSTICK
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37: NAND
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38: USB0
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39: USB1
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40: USB2
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41: SCR
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42: CSI0
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43: CSI1
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44: LCDCTRL0
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45: LCDCTRL1
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46: MP
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47: DEFEBE0
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48: DEFEBE1
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49: PMU
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50: SPI3
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51: TZASC
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52: PATA
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53: VE
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54: SS
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55: EMAC
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56: SATA
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57: GPS
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58: HDMI
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59: TVE
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60: ACE
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61: TVD
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62: PS2_0
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63: PS2_1
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64: USB3
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65: USB4
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66: PLE_PFM
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67: TIMER4
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68: TIMER5
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69: GPU_GP
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70: GPU_GPMMU
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71: GPU_PP0
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72: GPU_PPMMU0
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73: GPU_PMU
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74: GPU_RSV0
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75: GPU_RSV1
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76: GPU_RSV2
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77: GPU_RSV3
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78: GPU_RSV4
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79: GPU_RSV5
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80: GPU_RSV6
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82: SYNC_TIMER0
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83: SYNC_TIMER1
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Example:
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intc: interrupt-controller {
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compatible = "allwinner,sunxi-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
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@ -0,0 +1,150 @@
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/*
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* Allwinner A1X SoCs IRQ chip driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/sunxi.h>
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#define SUNXI_IRQ_VECTOR_REG 0x00
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#define SUNXI_IRQ_PROTECTION_REG 0x08
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#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
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#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
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#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
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#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
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#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
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static void __iomem *sunxi_irq_base;
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static struct irq_domain *sunxi_irq_domain;
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void sunxi_irq_ack(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
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writel(val | (1 << irq_off),
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sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
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}
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static void sunxi_irq_mask(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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writel(val & ~(1 << irq_off),
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sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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}
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static void sunxi_irq_unmask(struct irq_data *irqd)
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{
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unsigned int irq = irqd_to_hwirq(irqd);
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unsigned int irq_off = irq % 32;
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int reg = irq / 32;
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u32 val;
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val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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writel(val | (1 << irq_off),
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sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
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}
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static struct irq_chip sunxi_irq_chip = {
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.name = "sunxi_irq",
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.irq_ack = sunxi_irq_ack,
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.irq_mask = sunxi_irq_mask,
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.irq_unmask = sunxi_irq_unmask,
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};
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static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &sunxi_irq_chip,
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handle_level_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops sunxi_irq_ops = {
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.map = sunxi_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init sunxi_of_init(struct device_node *node,
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struct device_node *parent)
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{
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sunxi_irq_base = of_iomap(node, 0);
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if (!sunxi_irq_base)
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panic("%s: unable to map IC registers\n",
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node->full_name);
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/* Disable all interrupts */
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writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
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writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
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writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
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/* Mask all the interrupts */
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writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
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writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
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writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
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/* Clear all the pending interrupts */
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writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
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writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
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writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
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/* Enable protection mode */
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writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
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/* Configure the external interrupt source type */
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writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
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sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
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&sunxi_irq_ops, NULL);
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if (!sunxi_irq_domain)
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panic("%s: unable to create IRQ domain\n", node->full_name);
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return 0;
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}
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static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
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{ .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
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};
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void __init sunxi_init_irq(void)
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{
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of_irq_init(sunxi_irq_dt_ids);
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}
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asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
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{
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u32 irq, hwirq;
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hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
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while (hwirq != 0) {
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irq = irq_find_mapping(sunxi_irq_domain, hwirq);
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handle_IRQ(irq, regs);
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hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
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}
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}
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/*
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* Copyright 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_IRQCHIP_SUNXI_H
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#define __LINUX_IRQCHIP_SUNXI_H
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#include <asm/exception.h>
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extern void sunxi_init_irq(void);
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extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
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struct pt_regs *regs);
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#endif
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