ath9k_hw: add all the AR9003 PHY callbacks
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
c16fcb49b3
commit
af914a9ffd
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@ -225,7 +225,30 @@ static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
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static void ar9003_hw_init_bb(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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u32 synthDelay;
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/*
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* Wait for the frequency synth to settle (synth goes on
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* via AR_PHY_ACTIVE_EN). Read the phy active delay register.
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* Value is in 100ns increments.
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*/
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synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
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if (IS_CHAN_B(chan))
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synthDelay = (4 * synthDelay) / 22;
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else
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synthDelay /= 10;
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/* Activate the PHY (includes baseband activate + synthesizer on) */
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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/*
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* There is an issue if the AP starts the calibration before
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* the base band timeout completes. This could result in the
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* rx_clear false triggering. As a workaround we add delay an
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* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
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* does not happen.
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*/
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udelay(synthDelay + BASE_ACTIVATE_DELAY);
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}
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void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
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@ -385,46 +408,301 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
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static void ar9003_hw_set_rfmode(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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u32 rfMode = 0;
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if (chan == NULL)
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return;
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rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
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? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
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if (IS_CHAN_A_5MHZ_SPACED(chan))
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rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
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REG_WRITE(ah, AR_PHY_MODE, rfMode);
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}
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static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
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{
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/* TODO */
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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}
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static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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u32 coef_scaled, ds_coef_exp, ds_coef_man;
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u32 clockMhzScaled = 0x64000000;
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struct chan_centers centers;
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/*
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* half and quarter rate can divide the scaled clock by 2 or 4
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* scale for selected channel bandwidth
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*/
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if (IS_CHAN_HALF_RATE(chan))
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clockMhzScaled = clockMhzScaled >> 1;
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else if (IS_CHAN_QUARTER_RATE(chan))
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clockMhzScaled = clockMhzScaled >> 2;
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/*
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* ALGO -> coef = 1e8/fcarrier*fclock/40;
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* scaled coef to provide precision for this floating calculation
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*/
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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coef_scaled = clockMhzScaled / centers.synth_center;
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ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
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&ds_coef_exp);
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REG_RMW_FIELD(ah, AR_PHY_TIMING3,
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AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
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REG_RMW_FIELD(ah, AR_PHY_TIMING3,
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AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
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/*
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* For Short GI,
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* scaled coeff is 9/10 that of normal coeff
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*/
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coef_scaled = (9 * coef_scaled) / 10;
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ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
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&ds_coef_exp);
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/* for short gi */
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REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
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AR_PHY_SGI_DSC_MAN, ds_coef_man);
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REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
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AR_PHY_SGI_DSC_EXP, ds_coef_exp);
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}
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static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
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{
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/* TODO */
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return false;
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REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
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return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
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AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
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}
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/*
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* Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
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* Read the phy active delay register. Value is in 100ns increments.
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*/
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static void ar9003_hw_rfbus_done(struct ath_hw *ah)
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{
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/* TODO */
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u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
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if (IS_CHAN_B(ah->curchan))
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synthDelay = (4 * synthDelay) / 22;
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else
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synthDelay /= 10;
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udelay(synthDelay + BASE_ACTIVATE_DELAY);
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REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
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}
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/*
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* Set the interrupt and GPIO values so the ISR can disable RF
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* on a switch signal. Assumes GPIO port and interrupt polarity
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* are set prior to call.
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*/
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static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
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{
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/* TODO */
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/* Connect rfsilent_bb_l to baseband */
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
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/* Set input mux for rfsilent_bb_l to GPIO #0 */
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REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
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AR_GPIO_INPUT_MUX2_RFSILENT);
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/*
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* Configure the desired GPIO port for input and
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* enable baseband rf silence.
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*/
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ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
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REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
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}
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static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
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{
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/* TODO */
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u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
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if (value)
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v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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else
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v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
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REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
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}
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static bool ar9003_hw_ani_control(struct ath_hw *ah,
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enum ath9k_ani_cmd cmd, int param)
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{
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/* TODO */
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return false;
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struct ar5416AniState *aniState = ah->curani;
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struct ath_common *common = ath9k_hw_common(ah);
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switch (cmd & ah->ani_function) {
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case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
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u32 level = param;
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if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)ARRAY_SIZE(ah->totalSizeDesired));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
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AR_PHY_DESIRED_SZ_TOT_DES,
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ah->totalSizeDesired[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC,
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AR_PHY_AGC_COARSE_LOW,
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ah->coarse_low[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC,
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AR_PHY_AGC_COARSE_HIGH,
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ah->coarse_high[level]);
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REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
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if (level > aniState->noiseImmunityLevel)
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ah->stats.ast_ani_niup++;
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else if (level < aniState->noiseImmunityLevel)
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ah->stats.ast_ani_nidown++;
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aniState->noiseImmunityLevel = level;
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break;
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}
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case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
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const int m1ThreshLow[] = { 127, 50 };
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const int m2ThreshLow[] = { 127, 40 };
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const int m1Thresh[] = { 127, 0x4d };
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const int m2Thresh[] = { 127, 0x40 };
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const int m2CountThr[] = { 31, 16 };
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const int m2CountThrLow[] = { 63, 48 };
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u32 on = param ? 1 : 0;
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
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m1ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
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m2ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
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m2CountThrLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
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if (on)
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REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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else
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REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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if (!on != aniState->ofdmWeakSigDetectOff) {
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if (on)
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ah->stats.ast_ani_ofdmon++;
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else
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ah->stats.ast_ani_ofdmoff++;
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aniState->ofdmWeakSigDetectOff = !on;
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}
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break;
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}
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case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
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const int weakSigThrCck[] = { 8, 6 };
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u32 high = param ? 1 : 0;
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REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
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AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
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weakSigThrCck[high]);
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if (high != aniState->cckWeakSigThreshold) {
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if (high)
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ah->stats.ast_ani_cckhigh++;
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else
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ah->stats.ast_ani_ccklow++;
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aniState->cckWeakSigThreshold = high;
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}
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break;
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}
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case ATH9K_ANI_FIRSTEP_LEVEL:{
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const int firstep[] = { 0, 4, 8 };
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u32 level = param;
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if (level >= ARRAY_SIZE(firstep)) {
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned) ARRAY_SIZE(firstep));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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AR_PHY_FIND_SIG_FIRSTEP,
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firstep[level]);
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if (level > aniState->firstepLevel)
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ah->stats.ast_ani_stepup++;
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else if (level < aniState->firstepLevel)
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ah->stats.ast_ani_stepdown++;
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aniState->firstepLevel = level;
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break;
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}
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case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
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const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
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u32 level = param;
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if (level >= ARRAY_SIZE(cycpwrThr1)) {
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ath_print(common, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned) ARRAY_SIZE(cycpwrThr1));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_TIMING5,
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AR_PHY_TIMING5_CYCPWR_THR1,
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cycpwrThr1[level]);
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if (level > aniState->spurImmunityLevel)
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ah->stats.ast_ani_spurup++;
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else if (level < aniState->spurImmunityLevel)
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ah->stats.ast_ani_spurdown++;
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aniState->spurImmunityLevel = level;
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break;
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}
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case ATH9K_ANI_PRESENT:
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break;
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default:
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ath_print(common, ATH_DBG_ANI,
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"invalid cmd %u\n", cmd);
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return false;
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}
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ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
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ath_print(common, ATH_DBG_ANI,
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"noiseImmunityLevel=%d, spurImmunityLevel=%d, "
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"ofdmWeakSigDetectOff=%d\n",
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aniState->noiseImmunityLevel,
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aniState->spurImmunityLevel,
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!aniState->ofdmWeakSigDetectOff);
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ath_print(common, ATH_DBG_ANI,
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"cckWeakSigThreshold=%d, "
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"firstepLevel=%d, listenTime=%d\n",
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aniState->cckWeakSigThreshold,
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aniState->firstepLevel,
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aniState->listenTime);
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ath_print(common, ATH_DBG_ANI,
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"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
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aniState->cycleCount,
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aniState->ofdmPhyErrCount,
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aniState->cckPhyErrCount);
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return true;
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}
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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