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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu updates from Greg Ungerer:
 "This one has a major restructuring of the non-mmu 68000 support.

  It merges all the related SoC types that use the original 68000 cpu
  core internally so they can share the same core code.  It also allows
  for supporting the original stand alone 68000 cpu in its own right.

  There is also a generalization of the clock support of the ColdFire
  parts, some merging of common ColdFire code, and a couple of bug fixes
  as well."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: modify clock code so it can be used by all ColdFire CPU types
  m68knommu: add clock definitions for 54xx ColdFire CPU types
  m68knommu: add clock definitions for 5407 ColdFire CPU types
  m68knommu: add clock definitions for 5307 ColdFire CPU types
  m68knommu: add clock definitions for 528x ColdFire CPU types
  m68knommu: add clock definitions for 527x ColdFire CPU types
  m68knommu: add clock definitions for 5272 ColdFire CPU types
  m68knommu: add clock definitions for 525x ColdFire CPU types
  m68knommu: add clock definitions for 5249 ColdFire CPU types
  m68knommu: add clock definitions for 523x ColdFire CPU types
  m68knommu: add clock definitions for 5206 ColdFire CPU types
  m68knommu: add clock creation support macro for other ColdFire CPUs
  m68k: fix unused variable warning in mempcy.c
  m68knommu: make non-MMU page_to_virt() return a void *
  m68knommu: merge ColdFire 5249 and 525x definitions
  m68knommu: disable MC68000 cpu target when MMU is selected
  m68knommu: allow for configuration of true 68000 based systems
  m68knommu: platform code merge for 68000 core cpus
This commit is contained in:
Linus Torvalds 2012-12-16 17:42:21 -08:00
parent 123df7ae0d 280ef31a00
commit aed606e3bc
38 changed files with 693 additions and 984 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/m68k/Kconfig.cpu
View File

@ -35,7 +35,8 @@ endchoice
if M68KCLASSIC
config M68000
bool
bool "MC68000"
depends on !MMU
select CPU_HAS_NO_BITFIELDS
select CPU_HAS_NO_MULDIV64
select CPU_HAS_NO_UNALIGNED

6
arch/m68k/Makefile
View File

@ -92,7 +92,7 @@ endif
head-y := arch/m68k/kernel/head.o
head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o
head-$(CONFIG_M68360) := arch/m68k/platform/68360/head.o
head-$(CONFIG_M68000) := arch/m68k/platform/68328/head.o
head-$(CONFIG_M68000) := arch/m68k/platform/68000/head.o
head-$(CONFIG_COLDFIRE) := arch/m68k/platform/coldfire/head.o
core-y += arch/m68k/kernel/ arch/m68k/mm/
@ -114,9 +114,7 @@ core-$(CONFIG_M68040) += arch/m68k/fpsp040/
core-$(CONFIG_M68060) += arch/m68k/ifpsp060/
core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/
core-$(CONFIG_M68360) += arch/m68k/platform/68360/
core-$(CONFIG_M68000) += arch/m68k/platform/68328/
core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/
core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/
core-$(CONFIG_M68000) += arch/m68k/platform/68000/
core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/

269
arch/m68k/include/asm/m5249sim.h
View File

@ -1,269 +0,0 @@
/****************************************************************************/
/*
* m5249sim.h -- ColdFire 5249 System Integration Module support.
*
* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m5249sim_h
#define m5249sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5249)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* The 5249 has a second MBAR region, define its address.
*/
#define MCF_MBAR2 0x80000000
/*
* Define the 5249 SIM register set addresses.
*/
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
#define MCFQSPI_SIZE 0x40 /* Register set size */
#define MCFQSPI_CS0 29
#define MCFQSPI_CS1 24
#define MCFQSPI_CS2 21
#define MCFQSPI_CS3 22
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/*
* General purpose IO registers (in MBAR2).
*/
#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
/*
* Define the base interrupt for the second interrupt controller.
* We set it to 128, out of the way of the base interrupts, and plenty
* of room for its 64 interrupts.
*/
#define MCFINTC2_VECBASE 128
#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 64
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/****************************************************************************/
#ifdef __ASSEMBLER__
/*
* The M5249C3 board needs a little help getting all its SIM devices
* initialized at kernel start time. dBUG doesn't set much up, so
* we need to do it manually.
*/
.macro m5249c3_setup
/*
* Set MBAR1 and MBAR2, just incase they are not set.
*/
movel #0x10000001,%a0
movec %a0,%MBAR /* map MBAR region */
subql #1,%a0 /* get MBAR address in a0 */
movel #0x80000001,%a1
movec %a1,#3086 /* map MBAR2 region */
subql #1,%a1 /* get MBAR2 address in a1 */
/*
* Move secondary interrupts to their base (128).
*/
moveb #MCFINTC2_VECBASE,%d0
moveb %d0,0x16b(%a1) /* interrupt base register */
/*
* Work around broken CSMR0/DRAM vector problem.
*/
movel #0x001F0021,%d0 /* disable C/I bit */
movel %d0,0x84(%a0) /* set CSMR0 */
/*
* Disable the PLL firstly. (Who knows what state it is
* in here!).
*/
movel 0x180(%a1),%d0 /* get current PLL value */
andl #0xfffffffe,%d0 /* PLL bypass first */
movel %d0,0x180(%a1) /* set PLL register */
nop
#if CONFIG_CLOCK_FREQ == 140000000
/*
* Set initial clock frequency. This assumes M5249C3 board
* is fitted with 11.2896MHz crystal. It will program the
* PLL for 140MHz. Lets go fast :-)
*/
movel #0x125a40f0,%d0 /* set for 140MHz */
movel %d0,0x180(%a1) /* set PLL register */
orl #0x1,%d0
movel %d0,0x180(%a1) /* set PLL register */
#endif
/*
* Setup CS1 for ethernet controller.
* (Setup as per M5249C3 doco).
*/
movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
movel %d0,0x8c(%a0)
movel #0x001f0021,%d0 /* CS1 size of 1Mb */
movel %d0,0x90(%a0)
movew #0x0080,%d0 /* CS1 = 16bit port, AA */
movew %d0,0x96(%a0)
/*
* Setup CS2 for IDE interface.
*/
movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
movel %d0,0x98(%a0)
movel #0x001f0001,%d0 /* CS2 size of 1MB */
movel %d0,0x9c(%a0)
movew #0x0080,%d0 /* CS2 = 16bit, TA */
movew %d0,0xa2(%a0)
movel #0x00107000,%d0 /* IDEconfig1 */
movel %d0,0x18c(%a1)
movel #0x000c0400,%d0 /* IDEconfig2 */
movel %d0,0x190(%a1)
movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
orl %d0,0xc(%a1) /* function GPIO19 */
orl %d0,0x8(%a1) /* enable GPIO19 as output */
orl %d0,0x4(%a1) /* de-assert IDE reset */
.endm
#define PLATFORM_SETUP m5249c3_setup
#endif /* __ASSEMBLER__ */
/****************************************************************************/
#endif /* m5249sim_h */

116
arch/m68k/include/asm/m525xsim.h
View File

@ -12,6 +12,11 @@
#define m525xsim_h
/****************************************************************************/
/*
* This header supports ColdFire 5249, 5251 and 5253. There are a few
* little differences between them, but most of the peripheral support
* can be used by all of them.
*/
#define CPU_NAME "COLDFIRE(m525x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
@ -65,6 +70,8 @@
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Secondary Interrupt Controller (in MBAR2)
@ -101,11 +108,17 @@
#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
#define MCFQSPI_SIZE 0x40 /* Register set size */
#ifdef CONFIG_M5249
#define MCFQSPI_CS0 29
#define MCFQSPI_CS1 24
#define MCFQSPI_CS2 21
#define MCFQSPI_CS3 22
#else
#define MCFQSPI_CS0 15
#define MCFQSPI_CS1 16
#define MCFQSPI_CS2 24
#define MCFQSPI_CS3 28
#endif
/*
* I2C module.
@ -115,6 +128,7 @@
#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
#define MCFI2C_SIZE1 0x20 /* Register set size */
/*
* DMA unit base addresses.
*/
@ -163,6 +177,7 @@
#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
@ -183,12 +198,111 @@
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 64
#ifdef CONFIG_M5249
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
#else
#define MCFGPIO_IRQ_MAX 7
#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
#endif
/****************************************************************************/
#ifdef __ASSEMBLER__
#ifdef CONFIG_M5249C3
/*
* The M5249C3 board needs a little help getting all its SIM devices
* initialized at kernel start time. dBUG doesn't set much up, so
* we need to do it manually.
*/
.macro m5249c3_setup
/*
* Set MBAR1 and MBAR2, just incase they are not set.
*/
movel #0x10000001,%a0
movec %a0,%MBAR /* map MBAR region */
subql #1,%a0 /* get MBAR address in a0 */
movel #0x80000001,%a1
movec %a1,#3086 /* map MBAR2 region */
subql #1,%a1 /* get MBAR2 address in a1 */
/*
* Move secondary interrupts to their base (128).
*/
moveb #MCFINTC2_VECBASE,%d0
moveb %d0,0x16b(%a1) /* interrupt base register */
/*
* Work around broken CSMR0/DRAM vector problem.
*/
movel #0x001F0021,%d0 /* disable C/I bit */
movel %d0,0x84(%a0) /* set CSMR0 */
/*
* Disable the PLL firstly. (Who knows what state it is
* in here!).
*/
movel 0x180(%a1),%d0 /* get current PLL value */
andl #0xfffffffe,%d0 /* PLL bypass first */
movel %d0,0x180(%a1) /* set PLL register */
nop
#if CONFIG_CLOCK_FREQ == 140000000
/*
* Set initial clock frequency. This assumes M5249C3 board
* is fitted with 11.2896MHz crystal. It will program the
* PLL for 140MHz. Lets go fast :-)
*/
movel #0x125a40f0,%d0 /* set for 140MHz */
movel %d0,0x180(%a1) /* set PLL register */
orl #0x1,%d0
movel %d0,0x180(%a1) /* set PLL register */
#endif
/*
* Setup CS1 for ethernet controller.
* (Setup as per M5249C3 doco).
*/
movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
movel %d0,0x8c(%a0)
movel #0x001f0021,%d0 /* CS1 size of 1Mb */
movel %d0,0x90(%a0)
movew #0x0080,%d0 /* CS1 = 16bit port, AA */
movew %d0,0x96(%a0)
/*
* Setup CS2 for IDE interface.
*/
movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
movel %d0,0x98(%a0)
movel #0x001f0001,%d0 /* CS2 size of 1MB */
movel %d0,0x9c(%a0)
movew #0x0080,%d0 /* CS2 = 16bit, TA */
movew %d0,0xa2(%a0)
movel #0x00107000,%d0 /* IDEconfig1 */
movel %d0,0x18c(%a1)
movel #0x000c0400,%d0 /* IDEconfig2 */
movel %d0,0x190(%a1)
movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
orl %d0,0xc(%a1) /* function GPIO19 */
orl %d0,0x8(%a1) /* enable GPIO19 as output */
orl %d0,0x4(%a1) /* de-assert IDE reset */
.endm
#define PLATFORM_SETUP m5249c3_setup
#endif /* CONFIG_M5249C3 */
#endif /* __ASSEMBLER__ */
/****************************************************************************/
#endif /* m525xsim_h */

9
arch/m68k/include/asm/mcfclk.h
View File

@ -8,7 +8,6 @@
struct clk;
#ifdef MCFPM_PPMCR0
struct clk_ops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
@ -23,6 +22,8 @@ struct clk {
};
extern struct clk *mcf_clks[];
#ifdef MCFPM_PPMCR0
extern struct clk_ops clk_ops0;
#ifdef MCFPM_PPMCR1
extern struct clk_ops clk_ops1;
@ -38,6 +39,12 @@ static struct clk __clk_##clk_bank##_##clk_slot = { \
void __clk_init_enabled(struct clk *);
void __clk_init_disabled(struct clk *);
#else
#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
static struct clk clk_##clk_ref = { \
.name = clk_name, \
.rate = clk_rate, \
}
#endif /* MCFPM_PPMCR0 */
#endif /* mcfclk_h */

5
arch/m68k/include/asm/mcfsim.h
View File

@ -24,10 +24,7 @@
#elif defined(CONFIG_M523x)
#include <asm/m523xsim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M5249)
#include <asm/m5249sim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M525x)
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
#include <asm/m525xsim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M527x)

2
arch/m68k/include/asm/page_no.h
View File

@ -26,7 +26,7 @@ extern unsigned long memory_end;
#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
#define page_to_virt(page) __va(((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET))
#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))

3
arch/m68k/lib/memcpy.c
View File

@ -10,7 +10,7 @@
void *memcpy(void *to, const void *from, size_t n)
{
void *xto = to;
size_t temp, temp1;
size_t temp;
if (!n)
return xto;
@ -47,6 +47,7 @@ void *memcpy(void *to, const void *from, size_t n)
for (; temp; temp--)
*lto++ = *lfrom++;
#else
size_t temp1;
asm volatile (
" movel %2,%3\n"
" andw #7,%3\n"

18
arch/m68k/platform/68000/Makefile Normal file
View File

@ -0,0 +1,18 @@
##################################################
#
# Makefile for 68000 core based cpus
#
# 2012.10.21, Luis Alves <ljalvs@gmail.com>
# Merged all 68000 based cpu's config
# files into a single directory.
#
# 68328, 68EZ328, 68VZ328
obj-y += entry.o ints.o timers.o
obj-$(CONFIG_M68328) += m68328.o
obj-$(CONFIG_M68EZ328) += m68EZ328.o
obj-$(CONFIG_M68VZ328) += m68VZ328.o
obj-$(CONFIG_ROM) += romvec.o
extra-y := head.o

0
arch/m68k/platform/68VZ328/bootlogo.h → arch/m68k/platform/68000/bootlogo-vz.h
View File

0
arch/m68k/platform/68328/bootlogo.h → arch/m68k/platform/68000/bootlogo.h
View File

0
arch/m68k/platform/68328/entry.S → arch/m68k/platform/68000/entry.S
View File

240
arch/m68k/platform/68000/head.S Normal file
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@ -0,0 +1,240 @@
/*
* head.S - Common startup code for 68000 core based CPU's
*
* 2012.10.21, Luis Alves <ljalvs@gmail.com>, Single head.S file for all
* 68000 core based CPU's. Based on the sources from:
* Coldfire by Greg Ungerer <gerg@snapgear.com>
* 68328 by D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
/*****************************************************************************
* UCSIMM and UCDIMM use CONFIG_MEMORY_RESERVE to reserve some RAM
*****************************************************************************/
#ifdef CONFIG_MEMORY_RESERVE
#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)-(CONFIG_MEMORY_RESERVE*0x100000)
#else
#define RAMEND (CONFIG_RAMBASE+CONFIG_RAMSIZE)
#endif
/*****************************************************************************/
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
#if defined(CONFIG_PILOT) || defined(CONFIG_INIT_LCD)
.global bootlogo_bits
#endif
/* Defining DEBUG_HEAD_CODE, serial port in 68x328 is inited */
/* #define DEBUG_HEAD_CODE */
#undef DEBUG_HEAD_CODE
.data
/*****************************************************************************
* RAM setup pointers. Used by the kernel to determine RAM location and size.
*****************************************************************************/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
__HEAD
/*****************************************************************************
* Entry point, where all begins!
*****************************************************************************/
_start:
/* Pilot need this specific signature at the start of ROM */
#ifdef CONFIG_PILOT
.byte 0x4e, 0xfa, 0x00, 0x0a /* bra opcode (jmp 10 bytes) */
.byte 'b', 'o', 'o', 't'
.word 10000
nop
moveq #0, %d0
movew %d0, 0xfffff618 /* Watchdog off */
movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
#endif /* CONFIG_PILOT */
movew #0x2700, %sr /* disable all interrupts */
/*****************************************************************************
* Setup PLL and wait for it to settle (in 68x328 cpu's).
* Also, if enabled, init serial port.
*****************************************************************************/
#if defined(CONFIG_M68328) || \
defined(CONFIG_M68EZ328) || \
defined(CONFIG_M68VZ328)
/* Serial port setup. Should only be needed if debugging this startup code. */
#ifdef DEBUG_HEAD_CODE
movew #0x0800, 0xfffff906 /* Ignore CTS */
movew #0x010b, 0xfffff902 /* BAUD to 9600 */
movew #0xe100, 0xfffff900 /* enable */
#endif /* DEBUG_HEAD */
#ifdef CONFIG_PILOT
movew #0x2410, 0xfffff200 /* PLLCR */
#else
movew #0x2400, 0xfffff200 /* PLLCR */
#endif
movew #0x0123, 0xfffff202 /* PLLFSR */
moveq #0, %d0
movew #16384, %d0 /* PLL settle wait loop */
_pll_settle:
subw #1, %d0
bne _pll_settle
#endif /* CONFIG_M68x328 */
/*****************************************************************************
* If running kernel from ROM some specific initialization has to be done.
* (Assuming that everything is already init'ed when running from RAM)
*****************************************************************************/
#ifdef CONFIG_ROMKERNEL
/*****************************************************************************
* Init chip registers (uCsimm specific)
*****************************************************************************/
#ifdef CONFIG_UCSIMM
moveb #0x00, 0xfffffb0b /* Watchdog off */
moveb #0x10, 0xfffff000 /* SCR */
moveb #0x00, 0xfffff40b /* enable chip select */
moveb #0x00, 0xfffff423 /* enable /DWE */
moveb #0x08, 0xfffffd0d /* disable hardmap */
moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
movew #0x8f00, 0xfffffc00 /* DRAM configuration */
movew #0x9667, 0xfffffc02 /* DRAM control */
movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
moveb #0x40, 0xfffff300 /* IVR */
movel #0x007FFFFF, %d0 /* IMR */
movel %d0, 0xfffff304
moveb 0xfffff42b, %d0
andb #0xe0, %d0
moveb %d0, 0xfffff42b
#endif
/*****************************************************************************
* Init LCD controller.
* (Assuming that LCD controller is already init'ed when running from RAM)
*****************************************************************************/
#ifdef CONFIG_INIT_LCD
#ifdef CONFIG_PILOT
moveb #0, 0xfffffA27 /* LCKCON */
movel #_start, 0xfffffA00 /* LSSA */
moveb #0xa, 0xfffffA05 /* LVPW */
movew #0x9f, 0xFFFFFa08 /* LXMAX */
movew #0x9f, 0xFFFFFa0a /* LYMAX */
moveb #9, 0xfffffa29 /* LBAR */
moveb #0, 0xfffffa25 /* LPXCD */
moveb #0x04, 0xFFFFFa20 /* LPICF */
moveb #0x58, 0xfffffA27 /* LCKCON */
moveb #0x85, 0xfffff429 /* PFDATA */
moveb #0xd8, 0xfffffA27 /* LCKCON */
moveb #0xc5, 0xfffff429 /* PFDATA */
moveb #0xd5, 0xfffff429 /* PFDATA */
movel #bootlogo_bits, 0xFFFFFA00 /* LSSA */
moveb #10, 0xFFFFFA05 /* LVPW */
movew #160, 0xFFFFFA08 /* LXMAX */
movew #160, 0xFFFFFA0A /* LYMAX */
#else /* CONFIG_PILOT */
movel #bootlogo_bits, 0xfffffA00 /* LSSA */
moveb #0x28, 0xfffffA05 /* LVPW */
movew #0x280, 0xFFFFFa08 /* LXMAX */
movew #0x1df, 0xFFFFFa0a /* LYMAX */
moveb #0, 0xfffffa29 /* LBAR */
moveb #0, 0xfffffa25 /* LPXCD */
moveb #0x08, 0xFFFFFa20 /* LPICF */
moveb #0x01, 0xFFFFFA21 /* -ve pol */
moveb #0x81, 0xfffffA27 /* LCKCON */
movew #0xff00, 0xfffff412 /* LCD pins */
#endif /* CONFIG_PILOT */
#endif /* CONFIG_INIT_LCD */
/*****************************************************************************
* Kernel is running from FLASH/ROM (XIP)
* Copy init text & data to RAM
*****************************************************************************/
moveal #_etext, %a0
moveal #_sdata, %a1
moveal #__bss_start, %a2
_copy_initmem:
movel %a0@+, %a1@+
cmpal %a1, %a2
bhi _copy_initmem
#endif /* CONFIG_ROMKERNEL */
/*****************************************************************************
* Setup basic memory information for kernel
*****************************************************************************/
movel #CONFIG_VECTORBASE,_ramvec /* set vector base location */
movel #CONFIG_RAMBASE,_rambase /* set the base of RAM */
movel #RAMEND, _ramend /* set end ram addr */
lea __bss_stop,%a1
movel %a1,_ramstart
/*****************************************************************************
* If the kernel is in RAM, move romfs to right above bss and
* adjust _ramstart to where romfs ends.
*
* (Do this only if CONFIG_MTD_UCLINUX is true)
*****************************************************************************/
#if defined(CONFIG_ROMFS_FS) && defined(CONFIG_RAMKERNEL) && \
defined(CONFIG_MTD_UCLINUX)
lea __bss_start, %a0 /* get start of bss */
lea __bss_stop, %a1 /* set up destination */
movel %a0, %a2 /* copy of bss start */
movel 8(%a0), %d0 /* get size of ROMFS */
addql #8, %d0 /* allow for rounding */
andl #0xfffffffc, %d0 /* whole words */
addl %d0, %a0 /* copy from end */
addl %d0, %a1 /* copy from end */
movel %a1, _ramstart /* set start of ram */
_copy_romfs:
movel -(%a0), -(%a1) /* copy dword */
cmpl %a0, %a2 /* check if at end */
bne _copy_romfs
#endif /* CONFIG_ROMFS_FS && CONFIG_RAMKERNEL && CONFIG_MTD_UCLINUX */
/*****************************************************************************
* Clear bss region
*****************************************************************************/
lea __bss_start, %a0 /* get start of bss */
lea __bss_stop, %a1 /* get end of bss */
_clear_bss:
movel #0, (%a0)+ /* clear each word */
cmpl %a0, %a1 /* check if at end */
bne _clear_bss
/*****************************************************************************
* Load the current task pointer and stack.
*****************************************************************************/
lea init_thread_union,%a0
lea THREAD_SIZE(%a0),%sp
jsr start_kernel /* start Linux kernel */
_exit:
jmp _exit /* should never get here */

2
arch/m68k/platform/68328/ints.c → arch/m68k/platform/68000/ints.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/m68knommu/platform/68328/ints.c
* ints.c - Generic interrupt controller support
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive

2
arch/m68k/platform/68328/config.c → arch/m68k/platform/68000/m68328.c
View File

@ -1,7 +1,7 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/68328/config.c
* m68328.c - 68328 specific config
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne

2
arch/m68k/platform/68EZ328/config.c → arch/m68k/platform/68000/m68EZ328.c
View File

@ -1,7 +1,7 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/68EZ328/config.c
* m68EZ328.c - 68EZ328 specific config
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne

4
arch/m68k/platform/68VZ328/config.c → arch/m68k/platform/68000/m68VZ328.c
View File

@ -1,7 +1,7 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/68VZ328/config.c
* m68VZ328.c - 68VZ328 specific config
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne
@ -28,7 +28,7 @@
#include <asm/bootstd.h>
#ifdef CONFIG_INIT_LCD
#include "bootlogo.h"
#include "bootlogo-vz.h"
#endif
/***************************************************************************/

2
arch/m68k/platform/68328/romvec.S → arch/m68k/platform/68000/romvec.S
View File

@ -1,5 +1,5 @@
/*
* linux/arch/m68knommu/platform/68328/romvec.S
* romvec.S - Vector table for 68000 cpus
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive

2
arch/m68k/platform/68328/timers.c → arch/m68k/platform/68000/timers.c
View File

@ -1,7 +1,7 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/68328/timers.c
* timers.c - Generic hardware timer support.
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne

21
arch/m68k/platform/68328/Makefile
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@ -1,21 +0,0 @@
#
# Makefile for arch/m68knommu/platform/68328.
#
model-y := ram
model-$(CONFIG_ROMKERNEL) := rom
head-y = head-$(model-y).o
head-$(CONFIG_PILOT) = head-pilot.o
head-$(CONFIG_DRAGEN2) = head-de2.o
obj-y += entry.o ints.o timers.o
obj-$(CONFIG_M68328) += config.o
obj-$(CONFIG_ROM) += romvec.o
extra-y := head.o
$(obj)/head.o: $(obj)/$(head-y)
ln -sf $(head-y) $(obj)/head.o
clean-files := $(obj)/head.o $(head-y)

128
arch/m68k/platform/68328/head-de2.S
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@ -1,128 +0,0 @@
#define MEM_END 0x00800000 /* Memory size 8Mb */
#undef CRT_DEBUG
.macro PUTC CHAR
#ifdef CRT_DEBUG
moveq #\CHAR, %d7
jsr putc
#endif
.endm
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
.data
/*
* Set up the usable of RAM stuff
*/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
.text
_start:
/*
* Setup initial stack
*/
/* disable all interrupts */
movew #0x2700, %sr
movel #-1, 0xfffff304
movel #MEM_END-4, %sp
PUTC '\r'
PUTC '\n'
PUTC 'A'
PUTC 'B'
/*
* Determine end of RAM
*/
movel #MEM_END, %a0
movel %a0, _ramend
PUTC 'C'
/*
* Move ROM filesystem above bss :-)
*/
moveal #__bss_start, %a0 /* romfs at the start of bss */
moveal #__bss_stop, %a1 /* Set up destination */
movel %a0, %a2 /* Copy of bss start */
movel 8(%a0), %d1 /* Get size of ROMFS */
addql #8, %d1 /* Allow for rounding */
andl #0xfffffffc, %d1 /* Whole words */
addl %d1, %a0 /* Copy from end */
addl %d1, %a1 /* Copy from end */
movel %a1, _ramstart /* Set start of ram */
1:
movel -(%a0), %d0 /* Copy dword */
movel %d0, -(%a1)
cmpl %a0, %a2 /* Check if at end */
bne 1b
PUTC 'D'
/*
* Initialize BSS segment to 0
*/
lea __bss_start, %a0
lea __bss_stop, %a1
/* Copy 0 to %a0 until %a0 == %a1 */
2: cmpal %a0, %a1
beq 1f
clrl (%a0)+
bra 2b
1:
PUTC 'E'
/*
* Load the current task pointer and stack
*/
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
PUTC 'F'
PUTC '\r'
PUTC '\n'
/*
* Go
*/
jmp start_kernel
/*
* Local functions
*/
#ifdef CRT_DEBUG
putc:
moveb %d7, 0xfffff907
1:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq 1b
rts
#endif

207
arch/m68k/platform/68328/head-pilot.S
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@ -1,207 +0,0 @@
/*
* linux/arch/m68knommu/platform/68328/head-pilot.S
* - A startup file for the MC68328
*
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
* (c) 1995, Dionne & Associates
* (c) 1995, DKG Display Tech.
*/
#define ASSEMBLY
#define IMMED #
#define DBG_PUTC(x) moveb IMMED x, 0xfffff907
.global _stext
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
.global bootlogo_bits
/*****************************************************************************/
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
.align 4
_ramvec:
.long 0
_rambase:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
.text
_start:
_stext:
#ifdef CONFIG_M68328
#ifdef CONFIG_PILOT
.byte 0x4e, 0xfa, 0x00, 0x0a /* Jmp +X bytes */
.byte 'b', 'o', 'o', 't'
.word 10000
nop
#endif
moveq #0, %d0
movew %d0, 0xfffff618 /* Watchdog off */
movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
movew #0x0800, 0xfffff906 /* Ignore CTS */
movew #0x010b, 0xfffff902 /* BAUD to 9600 */
movew #0x2410, 0xfffff200 /* PLLCR */
movew #0x123, 0xfffff202 /* PLLFSR */
#ifdef CONFIG_PILOT
moveb #0, 0xfffffA27 /* LCKCON */
movel #_start, 0xfffffA00 /* LSSA */
moveb #0xa, 0xfffffA05 /* LVPW */
movew #0x9f, 0xFFFFFa08 /* LXMAX */
movew #0x9f, 0xFFFFFa0a /* LYMAX */
moveb #9, 0xfffffa29 /* LBAR */
moveb #0, 0xfffffa25 /* LPXCD */
moveb #0x04, 0xFFFFFa20 /* LPICF */
moveb #0x58, 0xfffffA27 /* LCKCON */
moveb #0x85, 0xfffff429 /* PFDATA */
moveb #0xd8, 0xfffffA27 /* LCKCON */
moveb #0xc5, 0xfffff429 /* PFDATA */
moveb #0xd5, 0xfffff429 /* PFDATA */
moveal #0x00100000, %a3
moveal #0x100ffc00, %a4
#endif /* CONFIG_PILOT */
#endif /* CONFIG_M68328 */
movew #0x2700, %sr
lea %a4@(-4), %sp
DBG_PUTC('\r')
DBG_PUTC('\n')
DBG_PUTC('A')
moveq #0,%d0
movew #16384, %d0 /* PLL settle wait loop */
L0:
subw #1, %d0
bne L0
DBG_PUTC('B')
/* Copy command line from beginning of RAM (+16) to end of bss */
movel #CONFIG_VECTORBASE, %d7
addl #16, %d7
moveal %d7, %a0
moveal #__bss_stop, %a1
lea %a1@(512), %a2
DBG_PUTC('C')
/* Copy %a0 to %a1 until %a1 == %a2 */
L2:
movel %a0@+, %d0
movel %d0, %a1@+
cmpal %a1, %a2
bhi L2
/* Copy data+init segment from ROM to RAM */
moveal #_etext, %a0
moveal #_sdata, %a1
moveal #__init_end, %a2
DBG_PUTC('D')
/* Copy %a0 to %a1 until %a1 == %a2 */
LD1:
movel %a0@+, %d0
movel %d0, %a1@+
cmpal %a1, %a2
bhi LD1
DBG_PUTC('E')
moveal #__bss_start, %a0
moveal #__bss_stop, %a1
/* Copy 0 to %a0 until %a0 == %a1 */
L1:
movel #0, %a0@+
cmpal %a0, %a1
bhi L1
DBG_PUTC('F')
/* Copy command line from end of bss to command line */
moveal #__bss_stop, %a0
moveal #command_line, %a1
lea %a1@(512), %a2
DBG_PUTC('G')
/* Copy %a0 to %a1 until %a1 == %a2 */
L3:
movel %a0@+, %d0
movel %d0, %a1@+
cmpal %a1, %a2
bhi L3
movel #_sdata, %d0
movel %d0, _rambase
movel #__bss_stop, %d0
movel %d0, _ramstart
movel %a4, %d0
subl #4096, %d0 /* Reserve 4K of stack */
moveq #79, %d7
movel %d0, _ramend
pea 0
pea env
pea %sp@(4)
pea 0
DBG_PUTC('H')
#ifdef CONFIG_PILOT
movel #bootlogo_bits, 0xFFFFFA00
moveb #10, 0xFFFFFA05
movew #160, 0xFFFFFA08
movew #160, 0xFFFFFA0A
#endif /* CONFIG_PILOT */
DBG_PUTC('I')
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
DBG_PUTC('J')
DBG_PUTC('\r')
DBG_PUTC('\n')
jsr start_kernel
_exit:
jmp _exit
.data
env:
.long 0

141
arch/m68k/platform/68328/head-ram.S
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@ -1,141 +0,0 @@
.global __main
.global __rom_start
.global _rambase
.global _ramstart
.global splash_bits
.global _start
.global _stext
.global _edata
#define DEBUG
#define ROM_OFFSET 0x10C00000
#define STACK_GAURD 0x10
.text
_start:
_stext:
movew #0x2700, %sr /* Exceptions off! */
#if 0
/* Init chip registers. uCsimm specific */
moveb #0x00, 0xfffffb0b /* Watchdog off */
moveb #0x10, 0xfffff000 /* SCR */
movew #0x2400, 0xfffff200 /* PLLCR */
movew #0x0123, 0xfffff202 /* PLLFSR */
moveb #0x00, 0xfffff40b /* enable chip select */
moveb #0x00, 0xfffff423 /* enable /DWE */
moveb #0x08, 0xfffffd0d /* disable hardmap */
moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
movew #0x8f00, 0xfffffc00 /* DRAM configuration */
movew #0x9667, 0xfffffc02 /* DRAM control */
movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
moveb #0x40, 0xfffff300 /* IVR */
movel #0x007FFFFF, %d0 /* IMR */
movel %d0, 0xfffff304
moveb 0xfffff42b, %d0
andb #0xe0, %d0
moveb %d0, 0xfffff42b
moveb #0x08, 0xfffff907 /* Ignore CTS */
movew #0x010b, 0xfffff902 /* BAUD to 9600 */
movew #0xe100, 0xfffff900 /* enable */
#endif
movew #16384, %d0 /* PLL settle wait loop */
L0:
subw #1, %d0
bne L0
#ifdef DEBUG
moveq #70, %d7 /* 'F' */
moveb %d7,0xfffff907 /* No absolute addresses */
pclp1:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq pclp1
#endif /* DEBUG */
#ifdef DEBUG
moveq #82, %d7 /* 'R' */
moveb %d7,0xfffff907 /* No absolute addresses */
pclp3:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq pclp3
#endif /* DEBUG */
moveal #0x007ffff0, %ssp
moveal #__bss_start, %a0
moveal #__bss_stop, %a1
/* Copy 0 to %a0 until %a0 >= %a1 */
L1:
movel #0, %a0@+
cmpal %a0, %a1
bhi L1
#ifdef DEBUG
moveq #67, %d7 /* 'C' */
jsr putc
#endif /* DEBUG */
pea 0
pea env
pea %sp@(4)
pea 0
#ifdef DEBUG
moveq #70, %d7 /* 'F' */
jsr putc
#endif /* DEBUG */
lp:
jsr start_kernel
jmp lp
_exit:
jmp _exit
__main:
/* nothing */
rts
#ifdef DEBUG
putc:
moveb %d7,0xfffff907
pclp:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq pclp
rts
#endif /* DEBUG */
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
.align 4
_ramvec:
.long 0
_rambase:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
env:
.long 0

105
arch/m68k/platform/68328/head-rom.S
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@ -1,105 +0,0 @@
.global _start
.global _stext
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
#ifdef CONFIG_INIT_LCD
.global bootlogo_bits
#endif
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
.align 4
_ramvec:
.long 0
_rambase:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
.text
_start:
_stext: movew #0x2700,%sr
#ifdef CONFIG_INIT_LCD
movel #bootlogo_bits, 0xfffffA00 /* LSSA */
moveb #0x28, 0xfffffA05 /* LVPW */
movew #0x280, 0xFFFFFa08 /* LXMAX */
movew #0x1df, 0xFFFFFa0a /* LYMAX */
moveb #0, 0xfffffa29 /* LBAR */
moveb #0, 0xfffffa25 /* LPXCD */
moveb #0x08, 0xFFFFFa20 /* LPICF */
moveb #0x01, 0xFFFFFA21 /* -ve pol */
moveb #0x81, 0xfffffA27 /* LCKCON */
movew #0xff00, 0xfffff412 /* LCD pins */
#endif
moveal #RAMEND-CONFIG_MEMORY_RESERVE*0x100000 - 0x10, %sp
movew #32767, %d0 /* PLL settle wait loop */
1: subq #1, %d0
bne 1b
/* Copy data segment from ROM to RAM */
moveal #_etext, %a0
moveal #_sdata, %a1
moveal #_edata, %a2
/* Copy %a0 to %a1 until %a1 == %a2 */
1: movel %a0@+, %a1@+
cmpal %a1, %a2
bhi 1b
moveal #__bss_start, %a0
moveal #__bss_stop, %a1
/* Copy 0 to %a0 until %a0 == %a1 */
1:
clrl %a0@+
cmpal %a0, %a1
bhi 1b
movel #_sdata, %d0
movel %d0, _rambase
movel #__bss_stop, %d0
movel %d0, _ramstart
movel #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0
movel %d0, _ramend
movel #CONFIG_VECTORBASE, %d0
movel %d0, _ramvec
/*
* load the current task pointer and stack
*/
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
1: jsr start_kernel
bra 1b
_exit:
jmp _exit
putc:
moveb %d7,0xfffff907
1:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq 1b
rts
.data
env:
.long 0
.text

5
arch/m68k/platform/68EZ328/Makefile
View File

@ -1,5 +0,0 @@
#
# Makefile for arch/m68knommu/platform/68EZ328.
#
obj-y := config.o

5
arch/m68k/platform/68VZ328/Makefile
View File

@ -1,5 +0,0 @@
#
# Makefile for arch/m68k/platform/68VZ328.
#
obj-y := config.o

126
arch/m68k/platform/coldfire/clk.c
View File

@ -19,38 +19,59 @@
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
#ifndef MCFPM_PPMCR0
struct clk *clk_get(struct device *dev, const char *id)
{
return NULL;
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
unsigned long clk_get_rate(struct clk *clk)
{
return MCF_CLK;
}
EXPORT_SYMBOL(clk_get_rate);
#else
static DEFINE_SPINLOCK(clk_lock);
#ifdef MCFPM_PPMCR0
/*
* For more advanced ColdFire parts that have clocks that can be enabled
* we supply enable/disable functions. These must properly define their
* clocks in their platform specific code.
*/
void __clk_init_enabled(struct clk *clk)
{
clk->enabled = 1;
clk->clk_ops->enable(clk);
}
void __clk_init_disabled(struct clk *clk)
{
clk->enabled = 0;
clk->clk_ops->disable(clk);
}
static void __clk_enable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR0);
}
static void __clk_disable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR0);
}
struct clk_ops clk_ops0 = {
.enable = __clk_enable0,
.disable = __clk_disable0,
};
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR1);
}
static void __clk_disable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR1);
}
struct clk_ops clk_ops1 = {
.enable = __clk_enable1,
.disable = __clk_disable1,
};
#endif /* MCFPM_PPMCR1 */
#endif /* MCFPM_PPMCR0 */
struct clk *clk_get(struct device *dev, const char *id)
{
const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
@ -101,48 +122,3 @@ unsigned long clk_get_rate(struct clk *clk)
EXPORT_SYMBOL(clk_get_rate);
/***************************************************************************/
void __clk_init_enabled(struct clk *clk)
{
clk->enabled = 1;
clk->clk_ops->enable(clk);
}
void __clk_init_disabled(struct clk *clk)
{
clk->enabled = 0;
clk->clk_ops->disable(clk);
}
static void __clk_enable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR0);
}
static void __clk_disable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR0);
}
struct clk_ops clk_ops0 = {
.enable = __clk_enable0,
.disable = __clk_disable0,
};
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR1);
}
static void __clk_disable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR1);
}
struct clk_ops clk_ops1 = {
.enable = __clk_enable1,
.disable = __clk_disable1,
};
#endif /* MCFPM_PPMCR1 */
#endif /* MCFPM_PPMCR0 */

8
arch/m68k/platform/coldfire/intc-5249.c
View File

@ -21,7 +21,7 @@ static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
}
@ -29,13 +29,13 @@ static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(struct irq_data *d)
{
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
}
static struct irq_chip intc2_irq_gpio_chip = {
@ -50,7 +50,7 @@ static int __init mcf_intc2_init(void)
int irq;
/* GPIO interrupt sources */
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
irq_set_chip(irq, &intc2_irq_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
}

20
arch/m68k/platform/coldfire/m5206.c
View File

@ -16,6 +16,26 @@
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
NULL
};
/***************************************************************************/

28
arch/m68k/platform/coldfire/m523x.c
View File

@ -19,6 +19,34 @@
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_fec0,
NULL
};
/***************************************************************************/

28
arch/m68k/platform/coldfire/m5249.c
View File

@ -16,6 +16,26 @@
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
NULL
};
/***************************************************************************/
@ -28,8 +48,8 @@ static struct resource m5249_smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = MCFINTC2_GPIOIRQ6,
.end = MCFINTC2_GPIOIRQ6,
.start = MCF_IRQ_GPIO6,
.end = MCF_IRQ_GPIO6,
.flags = IORESOURCE_IRQ,
},
};
@ -75,8 +95,8 @@ static void __init m5249_smc91x_init(void)
gpio = readl(MCFSIM2_GPIOINTENABLE);
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
gpio = readl(MCFSIM2_INTLEVEL5);
writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
gpio = readl(MCFINTC2_INTPRI5);
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
}
#endif /* CONFIG_M5249C3 */

20
arch/m68k/platform/coldfire/m525x.c
View File

@ -16,6 +16,26 @@
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
NULL
};
/***************************************************************************/

26
arch/m68k/platform/coldfire/m5272.c
View File

@ -19,6 +19,7 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
@ -30,6 +31,31 @@ unsigned char ledbank = 0xff;
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcftmr2,
&clk_mcftmr3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_fec0,
NULL
};
/***************************************************************************/
static void __init m5272_uarts_init(void)
{
u32 v;

30
arch/m68k/platform/coldfire/m527x.c
View File

@ -20,6 +20,36 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_fec0,
&clk_fec1,
NULL
};
/***************************************************************************/

28
arch/m68k/platform/coldfire/m528x.c
View File

@ -21,6 +21,34 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_fec0,
NULL
};
/***************************************************************************/

20
arch/m68k/platform/coldfire/m5307.c
View File

@ -17,6 +17,7 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfwdebug.h>
#include <asm/mcfclk.h>
/***************************************************************************/
@ -28,6 +29,25 @@ unsigned char ledbank = 0xff;
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
NULL
};
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel) || \

20
arch/m68k/platform/coldfire/m5407.c
View File

@ -16,6 +16,26 @@
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
NULL
};
/***************************************************************************/

26
arch/m68k/platform/coldfire/m54xx.c
View File

@ -14,19 +14,45 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/clk.h>
#include <linux/bootmem.h>
#include <asm/pgalloc.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/m54xxsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
#include <asm/m54xxgpt.h>
#include <asm/mcfclk.h>
#ifdef CONFIG_MMU
#include <asm/mmu_context.h>
#endif
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfslt0,
&clk_mcfslt1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfuart3,
NULL
};
/***************************************************************************/
static void __init m54xx_uarts_init(void)
{
/* enable io pins */